Abstract: In accordance with an embodiment, a hinge system for a door of vehicle includes a hinge arm configured to be mounted between a vehicle door enclosing a vehicle compartment and a vehicle body frame surround a wall structure that defines the vehicle compartment; and a hinge shaft configured to provide an axis of rotation of the hinge arm, and configured to be located outside the wall structure.

Abstract: A tie hoop untying prevention device of the present invention may comprise: a body part provided in a shape of surrounding the outer side surface and the upper and lower surfaces of a tie hoop and coupled to the tie hoop; a pair of extension parts provided at opposite ends of the body part, respectively, and formed in directions different from each other; separation preventing parts provided on both side surfaces of the body part, respectively, to prevent separation of the tie hoop; and a tying part provided at each of the corners of the body part to prevent vertical and outward movements of the tie hoop when being coupled to the tie hoop.

Abstract: In accordance with an embodiment, a hinge system for a door of vehicle includes a hinge arm configured to be mounted between a vehicle door enclosing a vehicle compartment and a vehicle body frame surround a wall structure that defines the vehicle compartment; and a hinge shaft configured to provide an axis of rotation of the hinge arm, and configured to be located outside the wall structure.

Abstract: A tie hoop untying prevention device of the present invention may comprise: a body part provided in a shape of surrounding the outer side surface and the upper and lower surfaces of a tie hoop and coupled to the tie hoop; a pair of extension parts provided at opposite ends of the body part, respectively, and formed in directions different from each other; separation preventing parts provided on both side surfaces of the body part, respectively, to prevent separation of the tie hoop; and a tying part provided at each of the corners of the body part to prevent vertical and outward movements of the tie hoop when being coupled to the tie hoop.

Abstract: A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.

Abstract: A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is unrepairable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

Abstract: A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.

Abstract: A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write accesses for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Abstract: A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.

Abstract: A management server is provided. The management server includes a communication interface unit configured to receive user environment information from a plurality of wearable apparatuses located in a preset space, an analyzer configured to analyze an environment state of the preset space based on a plurality of pieces of the received user environment information regarding the plurality of wearable apparatuses and determines an operation state of a common device located in the preset space according to the analyzed environment state, and a controller configured to control the communication interface unit so as to operate the common device according to the determined operation state.

Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers , and provides the second timing information corresponding to the timing differences to the transceivers.

Abstract: A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

Abstract: A time synchronization slave apparatus and a method of determining a time synchronization period are disclosed. In the apparatus, a time synchronization processing unit performs a time synchronization operation and determines an offset and a rate used to correct local time error based on a calculated time error, a timer corrects the local time based on the determined offset and rate, a time error estimation unit estimates a time error in the local time during a present time synchronization period, and generates excess error information regarding an excess point at which the estimated time error exceeds a threshold allowable time error range, a time synchronization period determination unit determines a subsequent time synchronization period based on the excess error information, and a synchronization period information transmission unit transmits synchronization period information regarding the subsequent time synchronization period to a time synchronization master apparatus.

Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.

Abstract: A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. The compression device may select a compression scheme among a plurality of compression schemes based on at least one characteristic of the data of the first memory and a data processing combination selected among a plurality of data processing combinations between a series of data processing units of the first memory and a series of data processing units of the second memory, and may compress the data of the first memory according to the selected compression scheme.