Abstract: A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.

Abstract: A method for refreshing memory cells includes: reading data from a plurality of memory cells; and performing a write operation with a first data onto memory cells from which the first data is read among the plurality of memory cells.

Abstract: A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Abstract: A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Abstract: A semiconductor system includes a host and a media controller. The host may generate first host parities from first host data based on an error check matrix. The media controller may include a first input/output (I/O) circuit and a second I/O circuit. The media controller may generate first media data and first media parities based on the first host data and the first host parities. The first I/O circuit may generate, based on the error check matrix, first internal data by correcting errors in the first host data using the first host parities. The second I/O circuit may generate the first media data and the first media parities from the first internal data.

Abstract: A semiconductor system may be provided. The semiconductor system may include a first semiconductor device configured for outputting a transmission command and a transmission address, being inputted with and outputting transmission data, and generating an error flag signal when an error bit is included in the transmission data inputted in a read operation. The semiconductor system may include a second semiconductor device configured for storing the transmission address in a lookup table circuit when the error flag signal is enabled, and comparing the transmission address and a storage address stored in the lookup table circuit when the read operation is performed based on the transmission command and outputting the transmission data from the lookup table circuit.

Abstract: A memory system includes a memory device including a memory block, the memory block including a plurality of memory cell groups, an address translator that maps a logical address of a data to a physical address of the memory block, and a controller configured to divide the plurality of memory cell groups into a plurality of first memory cell groups and at least one second memory cell group, and control the address translator so that the address translator maps a logical address of a data to a physical address of the first memory cell groups of the memory block and not in the at least one second memory cell group and switches the at least one second memory cell group with a selected first memory cell group among the plurality of the first memory cell groups when a predetermined period of time elapses.

Abstract: Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A method for operating a memory device comprising a plurality of memory cells, the method may include: performing a first refresh operation comprising sequentially applying a recovery pulse to each of the plurality of memory cells and repeating the sequential application of the recovery pulse to each of the plurality of memory cells for a predetermined number of times; and performing a second refresh operation comprising sequentially re-writing data of each of the plurality of memory cells once after the first refresh operation is performed for the predetermined number of times.

Abstract: A method for operating a memory device comprising a plurality of memory cells, the method may include: performing a first refresh operation comprising sequentially applying a recovery pulse to each of the plurality of memory cells and repeating the sequential application of the recovery pulse to each of the plurality of memory cells for a predetermined number of times; and performing a second refresh operation comprising sequentially re-writing data of each of the plurality of memory cells once after the first refresh operation is performed for the predetermined number of times.

Abstract: A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.

Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

Abstract: A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.

Abstract: In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

Abstract: A memory module may include a first memory device configured to be controlled by a host memory controller, to transmit/receive data to/from the host memory controller in a first mode, and to transmit/receive data to/from a module memory controller in a second mode, a second memory device configured to be controlled by the module memory controller and to transmit/receive data to/from the module memory controller in the second mode, and the module memory controller configured to monitor control of the first memory device by the host memory controller, to exchange data such that the data is transmitted/received between the first memory device and the second memory device in the second mode, and to control the second memory device.

Abstract: A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

Abstract: A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.

Abstract: A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.