Abstract: A memory system may include a memory device suitable for storing data requested from a host, and a controller suitable for generating information on the data and transmitting/receiving the data and the information to/from the memory device through first and second data buses, respectively, during a first operation mode, or for transmitting/receiving the data to/from the memory device through one of the first and second data buses based on the data size, during a second operation mode.

Abstract: A method for operating a memory system includes: reading a data from a memory device; detecting and correcting an error of the data; when the error of the data is equal to or greater than a threshold value, deciding an address corresponding to memory cells from which the data is read in the memory device as a rewrite-requiring address; and rewriting the data of the memory cell corresponding to the rewrite-requiring address.

Abstract: A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Abstract: A robot cleaner is provided that includes a driver configured to move the robot cleaner, and a suction unit configured to suck foreign objects from a surface below the robot cleaner. The robot cleaner also includes a detector configured to capture images of regions disposed in front of the robot cleaner. The robot cleaner further includes a controller configured to control the detector to capture a first image of a region before cleaning, control the detector to capture a second image of the region after cleaning, and generate cleaning result information using the first and second images.

Abstract: A memory device may include one or more multi-channel memories and an interface unit suitable for interfacing the multi-channel memories. The interface unit may include a first data interface suitable for transferring data for the first channel of the multi-channel memories, a second data interface suitable for transferring data for the second channel of the multi-channel memories, and an extra data interface suitable for transferring data for a selected one of the first channel and the second channel so that the data is additionally transmitted.

Abstract: A memory controller may be provided. The memory controller may include a wear-leveler may be configured to determine whether execution of a swapping operation is required based on reception of a write command for a stack region.

Abstract: An address distribution apparatus includes an address distributor. The address distributor distributes addresses of a plurality of memory cells in a memory device to prevent at least two successive write operations from being applied to at least two adjacent memory cells sharing any one of a plurality of word lines or any one of a plurality of bit lines among the plurality of memory cells. The at least two write operations are performed in response to write requests outputted from a host, respectively.

Abstract: In an embodiment of the present disclosure, a memory module may be provided. In an embodiment of the present disclosure, a system may be provided. In an embodiment of the present disclosure, an operation of a system and memory module may be provided. The memory module may include a plurality of ranks in which a defragmentation operation of a memory is performed based on entrance of a low-power operation mode, and a vacant region of the memory is powered off based on entrance of a self-refresh mode after the defragmentation operation is ended. The memory module may include a page table of which data are updated based on an ending of the defragmentation operation of the memory.

Abstract: Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

Abstract: A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

Abstract: A memory apparatus and a method of wear-leveling of a memory apparatus may be provided. The memory apparatus may include a memory having a plurality of storage blocks and a plurality of free blocks. The memory apparatus may include a memory controller configured for performing a first global wear-leveling to move data of a first storage block, which is a hot block among the storage blocks, to a first free block among the free blocks. The memory apparatus may include a memory controller configured for remapping a result of a logic operation of a logical page address of each of the pages in the first storage block and a first security refresh key to a physical page address of each of the pages in the first free block.

Abstract: A nonvolatile memory system may include a nonvolatile memory device, a delegate page attacker, and a health status analyzer. The nonvolatile memory device may include at least one memory block including a plurality of storage pages and a delegate page. The delegate page attacker may be configured to attack a bit of the delegate page at the same corresponding location as a bit of the storage page in which an error occurs. The health status analyzer may be configured to perform write and read operations for the delegate page and analyzes error information occurred in the write and read operations to determine whether the nonvolatile memory device is in a failure status.

Abstract: A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.

Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

Abstract: A semiconductor system may include: a command queue suitable for storing a plurality of requests provided from a host according to rank and bank information of the requests; one or more determination units suitable for determining requests having a same row address in response to row address information of the requests stored in the command queue; an arbitration unit suitable for scheduling the plurality of requests according to internal priorities of the requests; a monitoring unit suitable for providing the rank information and row hit information of the plurality of requests outputted according to the scheduling result of the arbitration unit, to the arbitration unit; a command generation unit suitable for generating a plurality of commands corresponding to and in response to the plurality of requests outputted according to the scheduling result of the arbitration unit; and a semiconductor memory device suitable for performing an internal operation in response to the command, wherein the arbitration unit r

Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

Abstract: A data transmission and reception system may include: a data transmission apparatus configured to generate N Tx signals having discrete levels using N binary data, and output the N Tx signals to N single-ended signal lines, respectively, where N is a natural number equal to or larger than 2; and a data reception apparatus configured to receive the N Tx signals transmitted in parallel through the single-ended signal lines, and restore the N binary data by comparing the received N Tx signals to each other.

Abstract: a semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.

Abstract: A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.

Abstract: A test apparatus may include transceivers and a global de-skew circuit. In a training mode, the transceivers provide first timing information obtained by delaying a first data signal in the range of up to a preset unit interval based on a clock signal and receive second timing information corresponding to timing differences between a slowest transceiver and the remaining transceivers. In an operation mode, the transceivers provide compensation data to a plurality of DUTs (Devices Under Test) substantially simultaneously. The compensation data may be obtained by delaying a second data signal by multiples of the preset unit interval in response to the second timing information. In the training mode, the global de-skew circuit receives the first timing information, calculates, using the first timing information, the timing differences between the slowest transceiver and the remaining transceivers, and provides the second timing information corresponding to the timing differences to the transceivers.