Abstract: Disclosed is a composition for treating arthritis containing a dibenzo-p-dioxin derivative as an active ingredient. This dibenzo-p-dioxin derivative is very effective in inhibiting NF-kB and AP-1 activity, alleviates the symptoms of degenerative arthritis and rheumatoid arthritis without irritating the skin or causing side effects, and can continue to exhibit improvement effects for a considerable period of time after discontinuation of treatment. Additionally, when the dibenzo-p-dioxin derivative is contained in liposomes, the composition of the invention exhibits much greater effects on treating arthritis by absorption through skin, and thus is useful for the treatment of degenerative arthritis and rheumatoid arthritis.

Abstract: Disclosed are a color correction apparatus for panorama video stitching and a method of selecting a reference image using the same. A method of selecting a reference image for color correction when stitching panorama video based on input images includes selecting an optimum reference image candidate from the input images based on standard deviations for overlapping regions between the input images, performing color correction on the input images based on the optimum reference image candidate, and validating the optimum reference image candidate based on the color-corrected input images.

Abstract: Provided are an apparatus and method for coding and decoding a multi-object audio signal. The apparatus includes a down-mixer for down-mixing the audio signals into one down-mixed audio signal and extracting supplementary information including header information and spatial cue information for each of the audio signals, a coder for coding the down-mixed audio signal, and a supplementary information coder for generating the supplementary information as a bit stream. The header information includes identification information for each of the audio signals and channel information for the audio signals.

Abstract: Disclosed is a dynamic load balancing system. The dynamic load balancing system includes a resource management master managing bare servers that do not execute services and having a hierarchical structure and a service master dynamically allocating the bare servers to a load balancing server or a service execution server or dynamically releasing the pre-allocated load balancing server or service execution server by the bare servers, in consideration of monitoring information on a state or performance of a server and service requirements to be provided.

Abstract: A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: Provided is a negative electrode active material comprising (a) a core including one or more non-carbon-based materials selected from the group consisting of silicon, nickel, germanium, and titanium, and (b) an organic polymer coating layer formed of a polymer compound having a content of a fluorine component of 50 wt % or more on a surface of the core.

Abstract: Provided are a method of tuning a coding rate and applying an unequal error protection for an adaptive video transmission, and a video transmission/reception apparatus using the method. The video transmission apparatus may include: a coding rate tuner to predict, as a channel capacity of a subsequent channel interval, an estimated channel capacity value fed back from the video reception apparatus, and to tune video and channel coding rates within the predicted channel capacity; a video encoder to perform video encoding of video frames at the tuned video coding rate, and to generate a video packet; and a forward error correction (FEC) encoder to apply the unequal error protection based on a length of the video packet and a type of the video frames included in the video packet, and to perform channel encoding of the video packet at the tuned channel coding rate to generate a bitstream.

Abstract: Disclosed herein is an electrode active material for a secondary battery, and more particularly to an electrode active material comprising a porous silicon oxide-based composite and the method for preparing a porous silicon oxide-based composite.

Abstract: Disclosed herein is a porous silicon-based electrode active material, comprising a silicon phase, a SiOx (0<x<2) phase and a silicon dioxide phase and having a porosity of 7-71%.

Abstract: A system for transmitting data includes a plurality of data lines configured to transmit the data and a transmitting chip configured to output the data to the data lines and perform a crosstalk prevention operation in response to a data pattern of the data to be transmitted through the data lines and array information of the data lines to prevent crosstalk from occurring in the data lines.

Abstract: A latency control circuit includes a clock delay configured to output a plurality of serial delay signals obtained by serially delaying an input clock signal with the same intervals, a deviation information generating unit configured to generate a deviation information on the basis of a delay value, which the clock signal undergoes in a chip, and latency information, a clock selector configured to output a plurality of clock selection signals based on the plurality of serial delay signals and the deviation information, a command signal processing unit configured to generate a read signal based on an input command signal, and output a variable delay duplication signal by variably delaying the read signal, and a latency shifter configured to output a latency signal by combining the plurality of clock selection signals with the variable delay duplication signal.

Abstract: A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.

Abstract: A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

Abstract: A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.

Abstract: The invention relates to method for estimating wireless channel status in wireless network, which is to be performed by client device connected to server for transmitting a video packet stream through a wired/wireless network, comprising: a step of estimating a bit error rate using additional information on a received video packet; and a step of estimating the channel capacity of the wireless network using the estimated bit error rate. The server receives, from the client device, feedback on the estimated channel capacity information or channel condition information of the wireless network, and adjusts the optimal video coding rate or the optimal source coding rate in a wireless network. Accordingly, the deterioration in the video quality of the video stream being received in the client device in real-time may be prevented to thereby improve the quality of service (QoS) of the video being received through a wireless network.

Abstract: A test circuit of a semiconductor apparatus includes a test temperature information generation section, an erroneous operation prevention unit, and a refresh cycle adjustment unit. The test temperature information generation section outputs test temperature information having a plurality of bits in a test operation mode, and irregularly changes logic values of the plurality of bits and transition time points of the logic values. The erroneous operation prevention unit generates a temperature compensation signal in response to the test temperature information. The refresh cycle adjustment unit changes a cycle of a reference refresh signal in response to the temperature compensation signal, and generates a refresh signal.

Abstract: A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.

Abstract: A clock generation circuit includes a delay line, which delays an input clock and generates a delayed clock, a delay modeling unit, which delays the delayed clock by a modeled delay value and generates a feedback clock, a phase detection unit, which compares phases of the input clock and the feedback clock and generates a phase detection signal, a filter unit, which receives the phase detection signal and generates phase information, generates an update signal when a difference between the numbers of phase detection signals with a first and a second level generated is greater than or equal to a threshold value, and generates the update signal after a lapse of a predetermined time when the difference is less than the threshold value, and a delay line control unit, which sets a delay value of the delay line in response to the update signal and the phase information.

Abstract: Provided is an anode including an anode active material including SiOx (0<x?1) and a carbon material having a surface coated with amorphous carbon, wherein a crystal orientation ratio is in a range of 0.07 to 0.17. A lithium secondary battery including the anode of the present invention may have improved life characteristics, low thickness change rate, and improved initial discharge capacity.