Patents by Inventor Yong Ju

Yong Ju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Input buffer circuit of semiconductor apparatus
    Patent number: 8339159
    Abstract: The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: December 25, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ji-Wang Lee, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Jae-Min Jang, Chang-Kun Park
  • Delay locked loop
    Patent number: 8319535
    Abstract: A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: November 27, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Min Jang, Yong-Ju Kim, Hae-Rang Choi
  • On-die termination circuit
    Patent number: 8319520
    Abstract: An on-die termination circuit includes a reference period signal generation circuit that generates a reference period signal according to a level of a reference voltage, a first period signal generation circuit that generates a first period signal according to a voltage level of a pad, a period comparison circuit that compares a period of the first period signal with a period of the reference period signal and count a plurality of driving signals, and a driver circuit that drives the pad in response to the plurality of driving signals.
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: November 27, 2012
    Assignee: SK Hynix Inc.
    Inventors: Yong Ju Kim, Hyung Soo Kim, Hae Rang Choi, Jae Min Jang
  • METHOD AND APPARATUS FOR CONTROL OF RANDERING MULTIOBJECT OR MULTICHANNEL AUDIO SIGNAL USING SPATIAL CUE
    Publication number: 20120294449
    Abstract: The present research relates to controlling rendering of multi-object or multi-channel audio signals. The present research provides a method and apparatus for controlling rendering of multi-object or multi-channel audio signals based on spatial cues in a process of decoding the multi-object or multi-channel audio signals. To achieve the purpose, the method suggested in the research controls rendering in a spatial cue domain in the process of decoding the multi-object or multi-channel audio signals.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 22, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Seung-Kwon Beack, Jeong-Il SEO, Dae-Young JANG, Tae-Jin LEE, Yong-Ju LEE, Jin-Woo HONG, Jin-Woong KIM
  • AUDIO AUTHORING APPARATUS AND AUDIO PLAYBACK APPARATUS FOR AN OBJECT-BASED AUDIO SERVICE, AND AUDIO AUTHORING METHOD AND AUDIO PLAYBACK METHOD USING SAME
    Publication number: 20120277894
    Abstract: An audio producing apparatus and an audio playing apparatus for an object-based audio service, and an audio producing method and an audio playing method using the same are provided. The producing apparatus and the audio playing apparatus supplies the object-based audio service, using audio object signals corresponding to a number of audio channels processable by the audio playing apparatus.
    Type: Application
    Filed: December 10, 2010
    Publication date: November 1, 2012
    Applicants: NSONIX, INC, Electronics and Telecommunications Research Institute
    Inventors: Yong Ju Lee, Tae Jin Lee, Kyeong Ok Kang, Jin Woong Kim, Chang Soo Lim
  • DELAY LOCKED LOOP
    Publication number: 20120268180
    Abstract: A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.
    Type: Application
    Filed: July 26, 2011
    Publication date: October 25, 2012
    Inventors: Jae-Min JANG, Yong-Ju Kim, Hae-Rang Choi
  • METHOD OF DRIVING A DISPLAY PANEL AND A DISPLAY APPARATUS PERFORMING THE METHOD
    Publication number: 20120256977
    Abstract: A method of driving a display panel includes driving a first sub area and a second sub area of a pixel part in a two-dimensional (2D) image mode, wherein a first luminance difference exists between the first and second sub areas in the 2D image mode, and driving the first sub area and the second sub area of the pixel part in a three-dimensional (3D) image mode, wherein a second luminance difference exists between the first and second sub areas in the 3D image mode, the second luminance difference being smaller than the first luminance difference.
    Type: Application
    Filed: September 23, 2011
    Publication date: October 11, 2012
    Inventors: Yong-Ju Jeong, Jong-Hee Na, Young-Min Choi, Jae-Kil Lee, Seung-Kuk Yun, Ji-Eun Jang
  • Semiconductor IC device having power-sharing and method of power-sharing thereof
    Patent number: 8283804
    Abstract: A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: October 9, 2012
    Assignee: SK hynix Inc.
    Inventors: Hyung-Soo Kim, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
  • Nanowire memory
    Patent number: 8283654
    Abstract: Provided is a nanowire memory including a source and a drain corresponding to the source, and a nano channel formed to connect the source to the drain. Here, the nano channel includes a nanowire electrically connecting the source to the drain according to voltages of the source and drain, and a nanodot formed on the nanowire and having a plurality of potentials capturing charges. Thus, the nanowire memory has a simple structure, thereby simplifying a process. It can generate multi current levels by adjusting several energy states using gates, operate as a volatile or non-volatile memory by adjusting the gates and the energy level, and include another gate configured to adjust the energy level, resulting in formation of a hybrid structure of volatile and non-volatile memories.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: October 9, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Han Young Yu, Byung Hoon Kim, Soon Young Oh, Yong Ju Yun, Yark Yeon Kim, Won Gi Hong
  • DRIVING APPARATUS AND DRIVING METHOD OF DISPLAY DEVICE
    Publication number: 20120249507
    Abstract: A driving apparatus and a driving method of a liquid crystal display according to an exemplary embodiment of the present invention may remove or reduce flicker caused by a kickback voltage according to an inversion driving mode of the liquid crystal display even though the inversion driving mode is changed.
    Type: Application
    Filed: September 23, 2011
    Publication date: October 4, 2012
    Inventors: JAE-SEOB CHUNG, Seung Rock Choi, Yong-Ju Jeong, Sung-Yeol Baek
  • CONDUCTIVE INK COMPOSITION, METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING CONDUCTIVE THIN LAYER USING THE SAME
    Publication number: 20120251736
    Abstract: Disclosed is a conductive ink composition, a manufacturing method thereof, and a manufacturing method of a conductive thin film using the same, and more specifically, a conductive ink composition is provided that includes composite metal nanoparticles including first metal nanoparticles and second metal nanoparticles, and a polymer matrix. The polymer matrix is a composition including a polymer and a solvent, the first metal nanoparticles and the second metal nanoparticles are different metals, and the content of the composite metal nanoparticles is about 20 to about 25 wt %, the content of the polymer is about 5 to about 10 wt %, and the content of the solvent is about 65 to about 75 wt %, based on the total weight of the composition.
    Type: Application
    Filed: September 29, 2011
    Publication date: October 4, 2012
    Applicant: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Jae-Min HONG, Yong-Won SONG, Yong-Ju JUNG, Hee-Dok CHOI, Won-Suk HAN, Hak-Sung KIM
  • Low power variable delay circuit
    Patent number: 8278981
    Abstract: A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: October 2, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hae-Rang Choi, Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
  • Phase detection circuit
    Patent number: 8265218
    Abstract: A phase detection circuit includes a phase frequency detector for comparing a first input signal and a second input signal and outputting a first phase comparison signal and a second phase comparison signal, and a sensing circuit for sensing a pulse width difference between the first phase comparison signal and the second phase comparison signal and outputting phase detection signals which have different logic values.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: September 11, 2012
    Assignee: SK hynix Inc.
    Inventors: Yong Ju Kim, Kun Woo Park, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Hyung Soo Kim, Tae Jin Hwang
  • Image forming apparatus and transfer device thereof
    Patent number: 8254808
    Abstract: An image forming apparatus and a transfer device thereof the transfer device including an intermediate transfer belt, at least one intermediate transfer belt roller to maintain tension in the intermediate transfer belt, transfer rollers to press the intermediate transfer belt to image carriers and a state changing device. The state changing device includes: a rotating shaft; a first cam member coupled to the rotating shaft and configured to move the intermediate transfer belt roller to reduce the tension applied to the intermediate transfer belt; and a second cam member coupled to the rotating shaft and configured to move at least one of the transfer rollers away from the intermediate transfer belt.
    Type: Grant
    Filed: June 10, 2009
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Ho Lee, Jeong Yong Ju, Byeong Hwa Ahn
  • 3D image generation apparatus and method
    Patent number: 8253733
    Abstract: A three-dimensional (3D) image generator and 3D image generation method scale a depth map or a two-dimensional (2D) image, perform a cross filtering to sharpen a blurred region on the depth map based on location information of the depth map and 2D image, and thus obtain a clearer depth map and provide a more graphical 3D image using the depth map.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Won Kim, Yong Ju Jung, Aron Baik, Du-Sik Park
  • DELAY LOCKED LOOP
    Publication number: 20120194239
    Abstract: A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks.
    Type: Application
    Filed: May 19, 2011
    Publication date: August 2, 2012
    Inventors: Jae-Min JANG, Yong-Ju KIM, Hae-Rang CHOI
  • Apparatus for transmitting signal in semiconductor integrated circuit
    Patent number: 8213531
    Abstract: An apparatus for transmitting a signal in a semiconductor integrated circuit includes a multilevel transmission control block that outputs a plurality of bits of an input signal in serial or parallel according to whether a multilevel transmission operation is performed or not, and a signal processing block that selectively performs the multilevel transmission operation according to a form of the input signal, which are output in serial or parallel from the multilevel transmission control block.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: July 3, 2012
    Assignee: SK hynix, Inc.
    Inventors: Hyung Soo Kim, Kun Woo Park, Yong Ju Kim, Jong Woon Kim, Hee Woong Song, Ic Su Oh, Tae Jin Hwang
  • INTERNAL SUPPLY VOLTAGE GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL SUPPLY VOLTAGE
    Publication number: 20120161859
    Abstract: An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator, and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage.
    Type: Application
    Filed: February 22, 2012
    Publication date: June 28, 2012
    Inventors: Yong-Ju Kim, Sung-Woo Han, Hee-Woong Song, Ic-Su Oh, Hyung-Soo Kim, Tae-Jin Hwang, Hae-Rang Choi, Ji-Wang Lee, Jae-Min Jang, Chang-Kun Park
  • OPERATING METHODS FOR VIRTUAL MACHINE SERVER AND NODE AND APPARATUSES THEREOF
    Publication number: 20120167086
    Abstract: Disclosed are operating methods of a server and a node, and apparatuses thereof, and more particularly, to operating methods of a virtual machine server and a virtual machine node, and apparatuses thereof. The operating method of the virtual machine server according to the exemplary embodiment of the present invention includes: generating index information of blocks for booting a virtual machine in a virtual machine image; generating list information of neighboring nodes for a target node; and transferring the index information and the list information to the target node.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 28, 2012
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventor: Yong Ju LEE
  • DYNAMIC LOAD BALANCING SYSTEM AND METHOD THEREOF
    Publication number: 20120166630
    Abstract: Disclosed is a dynamic load balancing system. The dynamic load balancing system includes a resource management master managing bare servers that do not execute services and having a hierarchical structure and a service master dynamically allocating the bare servers to a load balancing server or a service execution server or dynamically releasing the pre-allocated load balancing server or service execution server by the bare servers, in consideration of monitoring information on a state or performance of a server and service requirements to be provided.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 28, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Jung Hyun CHO, Hag Young KIM, Ok Gee MIN, Chang Soo KIM, Choon Seo PARK, Song Woo SOK, Yong Ju LEE, Jin Hwan JEONG, Joong Soo LEE