Abstract: Methods, systems, and devices for single crystal silicon cores for stacked memory cells are described. A memory device may be formed using silicon cores that are each associated with a set of multiple memory cells. Multiple silicon cores may extend along a first direction, and multiple sleeves of memory materials and conductive materials may be formed around each silicon core. Each sleeve of memory materials may be associated with a respective memory cell and each conductive material may be associated with a word line, such that each silicon core may be associated with multiple memory cells. The respective sleeves of memory materials and conductive materials may be formed from larger sleeves of material that may be etched into sections of the memory materials and the conductive materials along the silicon cores.

Abstract: A value chain knowledge discovery method under personalized customization is provided. The method comprises the following steps: defining a value topic for a given domain text, and extracting a value anchoring seed word; constructing a value semantic topological space according to the value anchoring seed word; expanding the value anchoring seed word to obtain an initial topic anchoring word set; updating the initial topic anchoring word to obtain an optimized topic anchoring word set; obtaining a multi-cluster net structure representation of a value semantic text by taking the optimized topic anchoring word as a constraint; and anchoring and constraining a plurality of cross-domain texts to construct a value chain knowledge graph.

Abstract: Devices and systems having a diffusion barrier for limiting diffusion of a phase change material including an electrode, a phase change material electrically coupled to the electrode, and a carbon and TiN (C:TiN) diffusion barrier disposed between the electrode and the phase change material to limit diffusion of the phase change material are disclosed and described.

Abstract: The invention relates to the field of permanent magnet materials, and discloses a composite permanent magnet material. The material is formed by splicing at least one permanent magnet material, with binding agent in between. The novel composite permanent magnet material that is formed by splicing different magnets greatly enriches the existing permanent magnet system and can completely replace the expensive rare metallic magnetic material. The composite permanent magnet material disclosed by the invention has high performances. The magnetic performance of the magnet can be regulated and controlled by adjusting the type and length of the magnets. In particular, the magnetic blank between the bonded NdFeB and the sintered NdFeB provides the designer and user of permanent magnetic motors with broader and flexible in material selection space and cost selection space.

Abstract: The invention relates to the field of permanent magnet materials, and discloses a composite permanent magnet material. The material is formed by splicing at least one permanent magnet material, with binding agent in between. The novel composite permanent magnet material that is formed by splicing different magnets greatly enriches the existing permanent magnet system and can completely replace the expensive rare metallic magnetic material. The composite permanent magnet material disclosed by the invention has high performances. The magnetic performance of the magnet can be regulated and controlled by adjusting the type and length of the magnets. In particular, the magnetic blank between the bonded NdFeB and the sintered NdFeB provides the designer and user of permanent magnetic motors with broader and flexible in material selection space and cost selection space.

Abstract: The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion.

Abstract: The invention included to methods of forming CoSi2, methods of forming field effect transistors, and methods of forming conductive contacts. In one implementation, a method of forming CoSi2 includes forming a substantially amorphous layer comprising MSix over a silicon-containing substrate, where “M” comprises at least some metal other than cobalt. A layer comprising cobalt is deposited over the substantially amorphous MSix-comprising layer. The substrate is annealed effective to diffuse cobalt of the cobalt-comprising layer through the substantially amorphous MSix-comprising layer and combine with silicon of the silicon-containing substrate to form CoSi2 beneath the substantially amorphous MSix-comprising layer. Other aspects and implementations are contemplated.

Abstract: The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion.

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.

Abstract: Some embodiments of the invention include structures and methods for a field emitter display device with a coating and an implantation layer underneath a surface of the emitter. Other embodiments are described and claimed.

Abstract: Structures and methods to ease electron emission and limit outgassing so as to inhibit degradation to the electron beam of a field emitter device are described. In one method to ease such electron emission, a layer of low relative dielectric constant material is formed under the surface of the field emitter tip. Another method is to coat the field emitter tip with a low relative dielectric constant substance or compound to form a layer and then cover that layer with a thin layer of the material of the field emitter tip.

Abstract: The invention includes an electrically conductive line, methods of forming electrically conductive lines, and methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines. In one implementation, a method of forming an electrically conductive line includes providing a silicon-comprising layer over a substrate. An electrically conductive layer is formed over the silicon-comprising layer. An MSixNy-comprising layer is formed over the electrically conductive layer, where “x” is from 0 to 3.0, “y” is from 0.5 to 10, and “M” is at least one of Ta, Hf, Mo, and W. An MSiz-comprising layer is formed over the MSixNy-comprising layer, where “z” is from 1 to 3.0. A TiSia-comprising layer is formed over the MSiz-comprising layer, where “a” is from 1 to 3.0.

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

Abstract: A method of forming a catalyst body by forming a first layer of hemispherical grain polysilicon over a substrate, and oxidizing at least a portion of the first layer to form a second layer of silica. Additionally, forming a third layer of nitride material over the second layer, and forming a catalyst material over the nitride layer, can be performed before annealing to form a catalyst body.

Abstract: A process is disclosed for manufacturing a film that is smooth and has large nitride grains of a diffusion barrier material. Under the process, a nitride of the diffusion barrier material is deposited by physical vapor deposition in an environment of nitrogen. The nitrogen content of the environment is selected at an operating level such that nitride nuclei of the diffusion barrier material are evenly distributed. A grain growth step is then conducted in the nitrogen environment to grow a film of large nitride grains of the diffusion barrier material. Also disclosed is a stack structure suitable for MOS memory circuits incorporating a lightly nitrided refractory metal silicide diffusion barrier with a covering of a nitride of a diffusion barrier material. The stack structure is formed in accordance with the diffusion barrier material nitride film manufacturing process and exhibits high thermal stability, low resistivity, long range agglomeration blocking, and high surface smoothness.

Abstract: A method of forming a capacitor includes forming a first capacitor electrode over a substrate. A substantially crystalline capacitor dielectric layer is formed over the first capacitor electrode. The substrate with the substantially crystalline capacitor dielectric layer is provided within a chemical vapor deposition reactor. Such substrate has an exposed substantially amorphous material. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor under conditions effective to substantially selectively deposit polysilicon on the substantially crystalline capacitor dielectric layer relative to the exposed substantially amorphous material, and the polysilicon is formed into a second capacitor electrode.

Abstract: A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSix)/TaSixNy/GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSix)/Ta5Si3/GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade gm (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.

Abstract: A method of depositing polysilicon includes positioning a substrate within a chemical vapor deposition reactor. The substrate has an exposed substantially crystalline region and an exposed substantially amorphous region. A gaseous precursor comprising silicon is fed to the chemical vapor deposition reactor to provide a reactive atmosphere under conditions effective to substantially selectively deposit polysilicon on the crystalline region relative to the amorphous region. The reactive atmosphere during the depositing consists essentially of a gaseous silane precursor.

Abstract: A method used to form a semiconductor device comprises forming a polysilicon layer, forming a conductive barrier layer on the polysilicon layer, then forming a conductive nitride layer on the conductive barrier layer. Next, a conductive amorphous layer is formed on the conductive barrier layer, and an elemental metal layer is formed on the conductive amorphous layer. Without the conductive amorphous layer the elemental metal layer would form on the conductive nitride layer as a small grained, high resistance layer, while it forms on the conductive amorphous layer as a large grained, low resistance layer. A semiconductor device which may be formed using this method is also described.

Abstract: Complementary transistors and methods of forming the complementary transistors on a semiconductor assembly are described. The transistors can be formed from a metal silicon compound deficient of silicon bonding atoms on a dielectric material overlying a semiconductor substrate conductively doped for PMOS and NMOS regions. The metal silicon compound overlying the NMOS region is converted to a metal silicon nitride and the metal silicon compound overlying the PMOS region is converted to a metal silicide. NMOS transistor gate electrodes comprising metal silicon nitride and PMOS transistor gate electrodes comprising metal silicide can be formed.