Abstract: A portable terminal includes a first housing, a second housing, and a sliding module. The second housing is slidably connected to the first housing such that the second housing slides longitudinally on the first housing to open or close a face of the first housing. The sliding module is interposed between the first housing and the second housing to slidably combine the second housing to the first housing. The sliding module includes a pair of guide rods and a guide plate. The guide rods are mounted spaced apart on the rear face of the second housing along a sliding direction of the second housing. The guide plate is fixed to a face of the first housing. The guide plate is slidably connected to the guide rods.

Abstract: A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge.

Abstract: Provided is an internal voltage generator for preventing an occurrence of leakage current while a charge pumping is not performed. The internal voltage generator includes: a charge pumping unit for pumping an external voltage to generate a high voltage higher than the external voltage; a level detecting unit for detecting a level drop of the high voltage with respect to a reference voltage and outputting a detection signal; an oscillating unit for generating an oscillation signal in response to the detection signal; a pumping control signal generating unit for controlling a driving of the charge pumping unit in response to the oscillation signal; and a charge pump controlling unit for precharging the charge pumping unit in response to the detection signal.

Abstract: The present invention is related to a negative voltage generating circuit for reliably providing the semiconductor integrated circuit (IC) with a negative voltage. An electric charge pumping device generates a negative voltage by pumping an electric charge to a predetermined level supplied to one of a first node and a second node. A controlling device provides first and second pumping clock signal being clocked alternately every predetermined interval in response to a level of the negative voltage. A pumping controller controls an amount of electric charge supplied to the first node and the second node in response to the first and second pumping clock signals. Further, a reset controller resets the first node and the second node of the electric charge pumping means as the level of the negative voltage when the first and second pumping clock signals are inactivated.

Abstract: A semiconductor memory device reduces power consumption with maintaining quality of an internal power voltage and a core voltage. The semiconductor memory device reduces power consumption with sufficiently maintaining a core voltage during precharge.

Abstract: The present invention provides a power voltage supplier for stably supplying a noise-free power voltage without increasing a size of a reservoir capacitor by employing a sharing scheme of the reservoir capacitor. The power voltage supplier of a semiconductor memory device includes: a first power voltage supply line for supplying a first power voltage; a second power voltage supply line for supplying a second power voltage; a first reservoir capacitor for supplying the first and the second power voltages stably; and a reservoir capacitor controller for selectively connecting the first reservoir capacitor to the first power voltage supply line or the second power voltage supply line.

Abstract: There is provided a semiconductor memory device comprising a fuse control circuit for providing with a plurality of fail word line addresses written in its own circuit in advance and outputting a redundancy signal representing that an input address is the same as one of the fail word line addresses, and a normal word line interruption signal, a redundancy word line controller for inputting the redundancy signal and activating a designated redundancy word line; and a normal word line controller, for activating a word line corresponding to the input word line address, which is operated or interrupted in response to the normal word line interruption signal, wherein the normal word line interruption signal has a first logic state (logic low) at a pre-charge interval or when a same address as one of the fail word line addresses is inputted, and has a second logic state (logic high) when a normal address is inputted, and the redundancy signal has a first logic state (logic low) when a same address as one of the fai

Abstract: An RF system integrated with an RF switching unit and an RF modulator unit.

Abstract: Television images to be digitally recorded are divided into blocks and the discrete cosine transform DCT of each block is taken. The DC coefficient of each DCT block is scalar-quantized, and its AC coefficients are classified-vector-quantized (CVQ). The square of the value that part or all the AC coefficients among horizontal AC coefficients including a first AC coefficient and vertical AC coefficients including a second AC coefficient, according to the zigzag scanning sequence of DCT block, are subtracted from a representative value of a preset reference class. Using a multilevel compression method, lowest level codes are vector-partitioned by P-units at equal intervals with respect to each classified DCT block, and code books of representative vectors corresponding to the partitioned vectors are provided.

Abstract: Disclosed is a digital image compression and decompression method and apparatus for dividing a supplied digital image signal into blocks of predetermined size, performing variable-length coding of the signal, separating the signal with respect to principle information and remaining information, and controlling the record format so that each type of information is alternately recorded on a recording medium in an equal interval whenever recording the compressed information and decompressing the information, according to the reverse order, during decoding. Also, the function for extracting an activity in two steps during coding and then controlling the permitted number of bits of the variable length coding is provided. Accordingly, the coding efficiency is improved and the circuitry is simplified so that the price of the end product can be lowered.

Abstract: A fixed bit rate compression encoding method for dividing a two-dimensional video signal into DCT blocks and encoding the transform coefficients of each DCT block at a certain compression rate. The DC coefficient of each DCT block is scalar-quantized by l bits, each DCT block is classified into m classes according to its edge direction, AC coefficients of the classified DCT blocks are approximated to n representative vectors set for each class and are vector-scalar-quantized by p-bit indices of each representative vector, and the number B of encoding bits per block is generated at a fixed bit rate according to the expression: B=l+log.sub.2 m+n.times.p.