Abstract: A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; a source, a drain, and at least one nanostructure layer, which are disposed on the semiconductor substrate; and a gate stack structure surrounding each nanostructure layer, where the at least one nanostructure layer is disposed between the source and the drain, each nanostructure layer comprises a first material layer and second material layers, the second material layers are disposed at two sides of the first material layer along a thickness direction of the first material layer, each of the first material layer and the second material layers is in contact with both the source and the drain, and at least a part of the second material layers is different from the first material layer in material.

Abstract: The semiconductor device includes a semiconductor substrate; and a first gate-all-around transistor and a second gate-all-around transistor formed on the semiconductor substrate and spaced apart from each other in a direction parallel to a surface of the semiconductor substrate. Each of the first gate-all-around transistor and the second gate-all-around transistor includes at least one nanostructure layer between a source region and a drain region. The nanostructure layer in the first gate-all-around transistor and the nanostructure layer in the second gate-all-around transistor are integrally formed. A thickness of each part of each nanostructure layer in the first gate-all-around transistor in a length direction of the nanostructure layer is less than a thickness of a corresponding nanostructure layer in the second gate-all-around transistor. A thickness of a gate stack in the first gate-all-around transistor is greater than a thickness of a gate stack in the second gate-all-around transistor.

Abstract: A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.

Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device comprises an n-channel GAA transistor and a p-channel GAA transistor, which are spaced apart. Each of the n-channel GAA transistor and the p-channel GAA transistor comprises a source, a drain, and at least one nanostructure layer located between the source and the drain. The p-channel GAA transistor further comprises a gate stack structure and a gate sidewall. In the p-channel GAA transistor, the at least one nanostructure layer comprises a channel portion that is covered by the gate stack structure and a connecting portion that is covered by the gate sidewall, and germanium content in the channel portion is greater than germanium content in the connecting portion and is greater than germanium content in the at least one nanostructure layer of the n-channel GAA transistor.

Abstract: A transistor and a manufacturing method. The transistor includes a semiconductor base substrate, an active structure, a dielectric structure, and a gate stack structure. The active structure is formed on the semiconductor base substrate. The active structure includes a source region, a drain region, and a channel region located between the source region and the drain region. The channel region includes at least two nanostructures stacked in a thickness direction of the semiconductor base substrate. In the channel region, a bottom nanostructure has a greater width than other nanostructures. The dielectric structure is formed between the semiconductor base substrate and the active structure. The dielectric structure is in contact with the bottom nanostructure. The gate stack structure is formed on a surface of the bottom nanostructure not in contact with the dielectric structure, and the gate stack surrounds a periphery of the other nanostructures.

Abstract: A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; an active structure disposed on the semiconductor substrate, where the active structure comprises a source, a drain, and a channel between the source and the drain; a doped epitaxial structure, where a portion of the semiconductor substrate beneath the channel is recessed to form a first groove, the first groove is fully filled with the doped epitaxial structure, and primary carriers of the doped epitaxial structure are opposite in polarity to primary carriers of the source and the drain; and a gate stack structure surrounding the channel, where a portion of the gate stack structure beneath the channel is disposed between the doped epitaxial structure and the channel.

Abstract: A gate-all-around transistor is provided, including: a semiconductor substrate, a nanostructure, a gate stack structure and a gate length defining structure. In a length direction of the nanostructure, each layer of nanostructure includes a source region, a drain region, and a channel region between the two. Materials of the source region and drain region include a first metal semiconductor compound. The gate stack structure surrounds the channel region. In a length direction of the gate stack structure, a sidewall of the gate stack structure is recessed relative to a sidewall of the channel region to form a recess, and the gate length defining structure is filled in the recess. The gate length defining structure is made of a second metal semiconductor compound, and a semiconductor material for making the second metal semiconductor compound is different from that for making the first metal semiconductor compound.

Abstract: A method and a device for producing medium-thickness plates with high thickness precision through a CVC steckel mill. The method includes the following: heating a blank in the heating furnace, and roughly descaling by the descaling machine; enabling the blank to enter the rolling mill, after multi-pass flat rolling, carrying out multi-pass rolling, carrying out linkage rolling of the rolling mill and the coiler furnaces in the rolling process, and enabling the rolling tension to reach a set value; controlling the temperatures of the coiler furnace to a set value in the coiling process; and in the rolling process, starting 30-70% of the original flow of cooling water of the working roll of the rolling mill; and after rolling is finished, finishing the production process through the laminar cooling system and the hot straightening machine respectively.

Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device includes: a first gate-all-around (GAA) transistor disposed in the first region, including a first nanowire or nanosheet of at least one first layer, the at least one first layer and the substrate form a first group, among which all pairs of adjacent layers are separated by first distances, respectively; and a second GAA transistor disposed in the second region, including a second nanowire or nanosheet of at least two second layers, the at least two second layers and the substrate form a second group, among which the second layers are separated by second distances, respectively; where a minimum first distance is greater than a maximum second distance, and a quantity of the at least one first layer is less than a quantity of the at least two second layers.

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source/drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.

Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.

Abstract: A system, method, and computer-readable medium are disclosed for management of a distributed web application firewall (WAF) cluster that supports one or more protected applications. A WAF cluster infrastructure is configured for the protected applications. The WAF cluster includes one or more WAFs that are used to route traffic directed to the protected applications. The WAF cluster infrastructure is validated as to be current and updated. The validated WAF cluster infrastructure is then used as routing service.

Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

Abstract: The present disclosure provides a cooperative access method, system, and architecture of an external storage.

Abstract: A web application firewall (WAF) receives an application request from a router, wherein the application request is directed to a web application, and wherein the web application firewall is associated with the web application. The WAF updates the application request to include a first header, wherein the first header includes a copy of a uniform resource locator of the application request, and updates the uniform resource locator to indicate an address of the web application firewall. The WAF analyzes the application request to determine whether the application request is secure, wherein the analysis is based on a rule, and in response to a determination that the application request is secure, updates the application request to include a second header, wherein the second header includes an encrypted signature.

Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.

Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.

Abstract: The disclosure provides a method for fabricating a semiconductor device, in which a core device of the semiconductor device employs a stacked nanowires or nanosheets structure, and an input/output device of the semiconductor device employs FinFET structure. The disclosure also provides a FinFET with an input/output device compatible with the stacked nanowires or nanosheets. The solution of the disclosure solves the problem that if the input/output device employs stacked nanowires or nanosheets device, it is difficult to fill a metal gate between two nanowires or nanosheets due to the thicker dielectric layer, and even if the metal gate is filled partially, the electrical performance of the input/output device is still poor.

Abstract: A system, method, and computer-readable medium are disclosed for management of a distributed web application firewall (WAF) cluster that supports one or more protected applications. A WAF cluster infrastructure is configured for the protected applications. The WAF cluster includes one or more WAFs that are used to route traffic directed to the protected applications. The WAF cluster infrastructure is validated as to be current and updated. The validated WAF cluster infrastructure is then used as routing service.