Patents by Inventor Yongliang Li

Yongliang Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180142205
    Abstract: The invention provides a device and the use thereof in a cell experiment in vitro. This device has a polydopamine layer-carboxymethyl chitosan layer-peptide layer structure, which is capable of regulating behaviors of human pluripotent stem cells and is useful in cell culture or a cell experiment in vitro.
    Type: Application
    Filed: December 9, 2015
    Publication date: May 24, 2018
    Applicant: Peking University School And Hospital of Stomatology
    Inventors: Shicheng Wei, Ping Zhou, Xiaohong Zhang, Yongliang Li, Mengke Wang
  • Patent number: 9934256
    Abstract: End of retention processing is provided. Included is: creating, using a content manager (CM), an end of retention policy for a content in a database management system (DBMS; and creating, based on the end of retention policy, a stored procedure in the DBMS for managing the end of retention policy.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tawei Hu, Iun V. Leong, Yongliang Li, Phong K. Truong
  • Patent number: 9934255
    Abstract: End of retention processing is provided. Included is: creating, using a content manager (CM), an end of retention policy for a content in a database management system (DBMS; and creating, based on the end of retention policy, a stored procedure in the DBMS for managing the end of retention policy.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: April 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tawei Hu, Iun V. Leong, Yongliang Li, Phong K. Truong
  • Patent number: 9906619
    Abstract: A controller receives a request from a user to store content in a target node of a plurality of nodes. A determination is made of a preferred node for the user, from a repository that maintains a correspondence between the user and the preferred node for storing the content for the user, wherein the preferred node is included in the plurality of nodes. Responsive to determining from that the determined preferred node is the target node, the controller transmits the request from the user to store the content, to the preferred node. Responsive to determining that the determined preferred node is not the target node, the controller transmits the request and an identification of the target node to the preferred node.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gerald E. Kozina, Yongliang Li, Masoud Madani, George F. Silva
  • Patent number: 9812440
    Abstract: This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: November 7, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Kenneth P. Snowdon, Taeghyun Kang, Yongliang Li
  • Patent number: 9774954
    Abstract: This document discusses, among other things, an impedance detection circuit, method, and integrated circuit, comprising a ramp-up current generation circuit and an impedance determining circuit, wherein the ramp-up current generation circuit is configured to input a ramp-up current including n breaks to a port of a device where the ramp-up current generation circuit is disposed, to which port an external device is connected, and wherein the impedance determining circuit is configured to detect an impedance of the external device in each break time period of the ramp-up current input by the ramp-up current generation circuit until the impedance of the external device is acquired by detection in the last break time period of the n breaks.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: September 26, 2017
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Peng Zhu, Kenneth O'Brien, Jianing Zhou, Yongliang Li
  • Publication number: 20170154037
    Abstract: Provided are techniques for movement readiness checking. It is determined whether each content object in a set of content objects is ready for movement. For each content object in the set of content objects that is determined to be ready for movement, an associated movement readiness indicator is set to indicate that the content object is ready to be moved. Then, each content object in the set of content objects is moved that has the associated movement readiness indicator set to indicate that the content object is ready to be moved.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Gerald E. Kozina, Yongliang Li, Masoud Madani, George F. Silva
  • Publication number: 20170154066
    Abstract: An approach to enable subscription to a remote content repository without a native subscription service based on a change monitor deployed near the remote content repository. The change monitor takes advantage of a change log associated with the content repository to determine when changes to the repository occur and compares the changes from the change log to a subscription list provided from a subscription datastore. When changes in the repository match the subscription list then the change monitor sends a change notice toward the subscriber. The change monitor manages the subscription list based on polling the subscription datastore and replies to change notices indicating notices for subscribed objects are no longer necessary.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Inventors: Hai Ji, Xu Hua Li, Yongliang Li, Yuan Yuan Li, Randal J. Richardt, Hailin Wang
  • Patent number: 9591421
    Abstract: This document discusses, among other things, a detection system configured to identify a type of a pole of a four-pole audio jack using first and second comparators. The detection system can include a bias circuit configured to bias a detection input coupled to the pole, and first and second comparators configured to compare the detection input to respective first and second thresholds to provide an indication of the type of the pole.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 7, 2017
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Seth M. Prentice, Julie Lynn Stultz, Yongliang Li, Graham L S Connolly, Shawn Barden
  • Publication number: 20170026484
    Abstract: A controller receives a request from a user to store content in a target node of a plurality of nodes. A determination is made of a preferred node for the user, from a repository that maintains a correspondence between the user and the preferred node for storing the content for the user, wherein the preferred node is included in the plurality of nodes. Responsive to determining from that the determined preferred node is the target node, the controller transmits the request from the user to store the content, to the preferred node. Responsive to determining that the determined preferred node is not the target node, the controller transmits the request and an identification of the target node to the preferred node.
    Type: Application
    Filed: July 23, 2015
    Publication date: January 26, 2017
    Inventors: Gerald E. Kozina, Yongliang Li, Masoud Madani, George F. Silva
  • Patent number: 9350337
    Abstract: The disclosure provides a clamp circuit and a method for clamping voltage. The clamp circuit includes: a first switch control unit, connected with the high-potential terminal of the first stage output of a comparator and configured to clamp the voltage of the high-potential terminal to VGate1 when the voltage of the high-potential terminal is lower than a first pre-set value V1, and a second switch control unit, connected to the low-potential terminal of the first stage output of the comparator and configured to clamp the voltage of the low-potential terminal to VGate2 when the voltage of the low-potential terminal is higher than a second pre-set value V2, wherein the voltages of the first stage output of the comparator are between VGND and VCC. By the disclosure, the output voltage swings of the first stage of the comparator are limited, and thereby the processing speed of the comparator is improved.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: May 24, 2016
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Lei Huang, Yongliang Li
  • Publication number: 20160064374
    Abstract: This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 3, 2016
    Inventors: Kenneth P. Snowdon, Taeghyun Kang, Yongliang Li
  • Publication number: 20150236503
    Abstract: This document discusses, among other things, an electro-static discharge (EDS) filtering circuit and method, a reset circuit, and an electronic device. The ESD filtering circuit comprises a first current dividing circuit and a second current dividing circuit which respectively share a current of a first power source signal and aggregate the shared currents to form a second power source signal upon filtering, wherein a voltage drop of the first current dividing circuit is constant and the second current dividing circuit is a pure resistor element circuit.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 20, 2015
    Inventors: Peng Zhu, Lei Huang, Yongliang Li
  • Publication number: 20150233859
    Abstract: This document discusses, among other things, an impedance detection circuit, method, and integrated circuit, comprising a ramp-up current generation circuit and an impedance determining circuit, wherein the ramp-up current generation circuit is configured to input a ramp-up current including n breaks to a port of a device where the ramp-up current generation circuit is disposed, to which port an external device is connected, and wherein the impedance determining circuit is configured to detect an impedance of the external device in each break time period of the ramp-up current input by the ramp-up current generation circuit until the impedance of the external device is acquired by detection in the last break time period of the n breaks.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 20, 2015
    Inventors: Peng Zhu, Kenneth O'Brien, Jianing Zhou, Yongliang Li
  • Publication number: 20150149102
    Abstract: The present invention provides an online monitoring circuit of the series compensation spark gap divider return circuit, said series compensation spark gap divider return circuit includes voltage equalization link and the voltage sampling link; Said voltage link includes the capacitor C which series said voltage equalization link; Said online monitoring circuit includes the voltage sampling input module, series compensation current input module and the compare module; Said sampling voltage input module after amplified the voltage of the two ends of the series capacitor C converts it into direct current signal Udivide voltage; Said series compensation current input module after amplified the current signal of said series capacitor converts it into direct current voltage signal UCT; Said compare module realizes online monitoring the running state of said series spark gap divider return circuit though comparing said Udivide voltage and said UCT.
    Type: Application
    Filed: May 2, 2013
    Publication date: May 28, 2015
    Inventors: Guofu Li, Hui Yu, Zhiyuan Li, Yongliang Li
  • Publication number: 20150134628
    Abstract: End of retention processing is provided. Included is: creating, using a content manager (CM), an end of retention policy for a content in a database management system (DBMS; and creating, based on the end of retention policy, a stored procedure in the DBMS for managing the end of retention policy.
    Type: Application
    Filed: June 17, 2014
    Publication date: May 14, 2015
    Inventors: Tawei Hu, Iun V. Leong, Yongliang Li, Phong K. Truong
  • Patent number: 8598002
    Abstract: A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: December 3, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Yongliang Li
  • Patent number: 8574977
    Abstract: The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method after conventional LOCOS or STI dielectric isolation is completed; depositing high-K gate dielectric and performing rapid thermal annealing; depositing a composite metal gate; depositing a barrier metal layer; depositing a polysilicon film and a hard mask and then performing photolithography and etching the hard mask; removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface oxide layer in sequence to form a gate stack structure of polysilicon film/barrier metal layer/metal gate/high-K gate dielectric; forming spacers, source/drain implantation in a conventional manner and performing rapid thermal annealing, whereby while source/drain dopants ar
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: November 5, 2013
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Qiuxia Xu, Yongliang Li
  • Patent number: 8530302
    Abstract: A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: September 10, 2013
    Assignee: The Institute of Microelectronics, Chinese Academy of Science
    Inventors: Qiuxia Xu, Yongliang Li, Gaobo Xu
  • Publication number: 20130078773
    Abstract: A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate.
    Type: Application
    Filed: November 22, 2011
    Publication date: March 28, 2013
    Inventors: Qiuxia Xu, Yongliang Li, Gaobo Xu