Abstract: The present invention provides an online monitoring circuit of the series compensation spark gap divider return circuit, said series compensation spark gap divider return circuit includes voltage equalization link and the voltage sampling link; Said voltage link includes the capacitor C which series said voltage equalization link; Said online monitoring circuit includes the voltage sampling input module, series compensation current input module and the compare module; Said sampling voltage input module after amplified the voltage of the two ends of the series capacitor C converts it into direct current signal Udivide voltage; Said series compensation current input module after amplified the current signal of said series capacitor converts it into direct current voltage signal UCT; Said compare module realizes online monitoring the running state of said series spark gap divider return circuit though comparing said Udivide voltage and said UCT.

Abstract: End of retention processing is provided. Included is: creating, using a content manager (CM), an end of retention policy for a content in a database management system (DBMS; and creating, based on the end of retention policy, a stored procedure in the DBMS for managing the end of retention policy.

Abstract: A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration.

Abstract: The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method after conventional LOCOS or STI dielectric isolation is completed; depositing high-K gate dielectric and performing rapid thermal annealing; depositing a composite metal gate; depositing a barrier metal layer; depositing a polysilicon film and a hard mask and then performing photolithography and etching the hard mask; removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface oxide layer in sequence to form a gate stack structure of polysilicon film/barrier metal layer/metal gate/high-K gate dielectric; forming spacers, source/drain implantation in a conventional manner and performing rapid thermal annealing, whereby while source/drain dopants ar

Abstract: A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate.

Abstract: A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate.

Abstract: The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface Si2/high-K gate dielectric/metal gate/poly-silicon/hard mask in sequence on a silicon substrate with device isolations formed thereon; 2): forming a resist pattern by the lithography; 3): etching the gate stack structure; and 4): immersing the resultant structure of the step 3) in an etching solution to remove the polymer, wherein the etching solution consists of HF, HCl and water, the ratio of HF by volume is 0.2˜1% and the ratio of HCl by volume is 5˜15%.

Abstract: The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method after conventional LOCOS or STI dielectric isolation is completed; depositing high-K gate dielectric and performing rapid thermal annealing; depositing a composite metal gate; depositing a barrier metal layer; depositing a polysilicon film and a hard mask and then performing photolithography and etching the hard mask; removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface oxide layer in sequence to form a gate stack structure of polysilicon film/barrier metal layer/metal gate/high-K gate dielectric; forming spacers, source/drain implantation in a conventional manner and performing rapid thermal annealing, whereby while source/drain dopants ar

Abstract: Providing search information is disclosed, including: receiving one or more user input search keywords; automatically determining a plurality of search channels based at least in part on the one or more user input search keywords; searching the determined plurality of search channels for information that is relevant to the one or more user input search keywords; and returning relevant information associated with the determined plurality of search channels.

Abstract: A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO2 on a silicon substrate; depositing a high K dielectric film on the interfacial layer; performing a rapid thermal anneal of the high K dielectric film; depositing a TaN metal gate electrode film on the high K dielectric film; depositing a polysilicon gate layer on the TaN metal gate electrode film, and then depositing a hard mask layer; patterning a photoresist mask, and performing an anisotropic etching of the hard mask layer; removing the photoresist mask, and etching the polysilicon by reactive ion etching with the hard mask as masking layer using a mixed gas of Cl2/HBr; and etching the TaN metal gate electrode/high K dielectric gate stack by reactive ion etching with the hard mask as masking layer using BCl3-based etchant gas.

Abstract: The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface SiO2/high-K gate dielectric/metal gate/poly-silicon/hard mask in sequence on a silicon substrate with device isolations formed thereon; 2): forming a resist pattern by the lithography; 3): etching the gate stack structure; and 4): immersing the resultant structure of the step 3) in an etching solution to remove the polymer, wherein the etching solution consists of HF, HCl and water, the ratio of HF by volume is 0.2˜1% and the ratio of HCl by volume is 5˜15%. According to the present invention, the wet chemical etching using a mixed solution of HF and HCl is adopted and thus it is possible to completely remove the polymer remained on both sides of the gate stack and on the surface of the silicon substrate under the room temperature.

Abstract: The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO2 interface layer, a high K dielectric layer, a Mo-based metal gate layer, an AlN barrier layer, a silicon gate layer and a hard mask in sequence on a semiconductor substrate; performing lithography on the semiconductor substrate with the SiO2 interface layer, the high K dielectric layer, the Mo-based metal gate layer, the AlN barrier layer, the silicon gate layer and the hard mask using a photoresist, and etching the hard mask; removing the photoresist, and performing an anisotropic etching for silicon gate with high selectivity to the underlying AlN barrier layer and metal gate by dry etching using the hard mask; performing an anisotropic etching for the AlN barrier layer, the Mo-based metal gate layer, and the high K dielectric layer by a dry etching.

Abstract: A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration.

Abstract: The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO2 interface layer, a high K dielectric layer, a Mo-based metal gate layer, an AlN barrier layer, a silicon gate layer and a hard mask in sequence on a semiconductor substrate; performing lithography on the semiconductor substrate with the SiO2 interface layer, the high K dielectric layer, the Mo-based metal gate layer, the AlN barrier layer, the silicon gate layer and the hard mask using a photoresist, and etching the hard mask; removing the photoresist, and performing an anisotropic etching for silicon gate with high selectivity to the underlying AlN barrier layer and metal gate by dry etching using the hard mask; performing an anisotropic etching for the AlN barrier layer, the Mo-based metal gate layer, and the high K dielectric layer by a dry etching.

Abstract: A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO2 on a silicon substrate; depositing a high K dielectric film on the interfacial layer; performing a rapid thermal anneal of the high K dielectric film; depositing a TaN metal gate electrode film on the high K dielectric film; depositing a polysilicon gate layer on the TaN metal gate electrode film, and then depositing a hard mask layer; patterning a photoresist mask, and performing an anisotropic etching of the hard mask layer; removing the photoresist mask, and etching the polysilicon by reactive ion etching with the hard mask as masking layer using a mixed gas of Cl2/HBr; and etching the TaN metal gate electrode/high K dielectric gate stack by reactive ion etching with the hard mask as masking layer using BCl3-based etchant gas.