Patents by Inventor Yong Liang

Yong Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080072961
    Abstract: A sensitized photovoltaic device (10) provides for a reduction of the charge recombination rate and charge transport time. The device (10) includes a first electrode (12) comprising a transparent conducting oxide and a plurality of carbon nanostructures (16) formed thereon. A first layer (18) is formed on the carbon nanostructure (16) and comprises a first conduction band level (44). A second layer (20) is formed on the first oxide (18) and comprises a second conduction band level (46) higher than the first conduction band level (44). A sensitizer (22) is formed on the second layer (20) and comprises a lowest unoccupied molecular orbital level (48) higher than the second conduction band level (46). An electrolyte (24) is positioned over the sensitizer (22), and a second electrode (26) comprising a transparent conducting oxide and a layer of catalyst is formed over the electrolyte (24).
    Type: Application
    Filed: September 26, 2006
    Publication date: March 27, 2008
    Inventors: Yong Liang, Jon J. Candelaria, Kurt W. Eisenbeiser, Yi Wei
  • Publication number: 20080037584
    Abstract: This invention presents a multimode xDSL line card adaptive activation method, comprising the following steps: A) A master controller is installed and configured with multiple templates based on the modes of operation supported by a line card, and forwards templates to said line card; B) The line card receives templates forwarded by the master controller and activates the line card communications chip; C) The communications chip communicates with the remote CPE and decides on a mode of operation according to a handshake protocol; D) The line card employs a corresponding template according to the mode of operation chosen in Step C, and practices circuit activation with the CPE. This invention solves the existing problems in current multimode xDSL technology of poor compatibility and inability to adapt effectively.
    Type: Application
    Filed: December 14, 2006
    Publication date: February 14, 2008
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Yong Liang, Haihong Wei, Binfeng Wang, Xinjun Zhang
  • Patent number: 7314956
    Abstract: The present invention provides a drug delivery vehicle that can improve the pharmacokinetics of pharmacological agents. The invention relates to a multifunctional carrier capable of delivering a carried material such as a pharmacological agent or genetic material to a recipient. The multifunctional carrier includes a multifunctional core and a plurality of adduct molecules bonded thereto. The molecular carrier has surface functional groups which can be associated with a carried material. The carried material can be associated with the molecular carrier through covalent interactions or ionic interactions. The polyvalent core can be ethylene-diamine tetraacetic acid (EDTA) or succinic acid. The invention also relates to methods for producing and using such molecules.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: January 1, 2008
    Assignee: Vaxim, Inc.
    Inventors: Frank Q. Li, Yong Liang Chu, Shuren Zhu, Jian-Tai Qiu, Wan-Ching Lai
  • Patent number: 7294247
    Abstract: The invention concerns to an electrophoretic separation device comprising a separation channel having at least one in- and outlet opening at the beginning and at the end of the channel and one electrode in the region of the inlet opening and one electrode in the region of the outlet opening. As well the invention concerns to a method for electrophoretic separation. The invention is characterized in that said separation channel is subdivided into at least two sections in series being coupled mutually by a joint providing an electrical connection means having a ion-conductive material separating said channel from a reservoir being apart the channel and provided with an electrode.
    Type: Grant
    Filed: October 25, 2000
    Date of Patent: November 13, 2007
    Assignees: Xiamen University, Institute for Biomedical Engineering IBMT
    Inventors: Zhao-Wu Tian, Hua-Shui Lin, Yong-Liang Zhou
  • Patent number: 7241691
    Abstract: Methods for fabricating high work function p-MOS device metal electrodes are provided. In one embodiment, a method is provided for producing a metal electrode including the steps of: providing a high k dielectric stack with an exposed surface; contacting the exposed surface of the high k dielectric stack with a vapor of a metal oxide wherein the metal oxide is selected from the group consisting of RuOx, IrOx, ReOx, MoOx, WOx, VOx, and PdOx; and contacting the exposed surface of the dielectric stack with a vapor of an additive selected from the group consisting of SiO2, Al2O3, HfO2, ZrO2, MgO, SrO, BaO, Y2O3, La2O3, and TiO2, whereby contacting the exposed surface of the dielectric stack with the vapor of the metal oxide and the vapor of the additive forms an electrode and wherein the additive is present at an amount between about 1% to about 50% by atomic weight percent in the electrode.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: July 10, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yong Liang, Clarence J. Tracy
  • Publication number: 20070147590
    Abstract: The present invention discloses a system for testing subscriber lines and method thereof. The system includes a broadband line testing control module and a remote terminal subscriber access control module located at a subscriber line that is located between the broadband line testing control module and a remote terminal unit. The broadband line testing control module sends a signal of disconnecting the subscriber line to the remote terminal subscriber access control module, and tests the subscriber line. The remote terminal subscriber access control module receives said signal from the broadband line testing control module, and controls the remote terminal unit to disconnect from or connect to the subscriber line based on said signal. With the system and method according to the present invention, not only the precision of subscriber line testing is guaranteed, but also the subscriber lines can be periodically tested without manual operation.
    Type: Application
    Filed: October 25, 2004
    Publication date: June 28, 2007
    Inventor: Yong Liang
  • Patent number: 7217643
    Abstract: Semiconductor structures, and methods for fabricating semiconductor structures, comprising high dielectric constant stacked structures are provided. A stacked dielectric structure (16) in accordance with one exemplary embodiment of the present invention has a first amorphous dielectric layer (18) comprising HfXZr1-XO2, where 0?X?1. An amorphous interlayer (20) overlies the first amorphous dielectric layer. The interlayer has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO4. A second amorphous dielectric layer (22) overlies the interlayer. The second amorphous dielectric layer comprises HfYZr1-YO2, where 0?Y?1. The stacked dielectric structure (16) has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO4.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: May 15, 2007
    Assignee: Freescale Semiconductors, Inc.
    Inventors: Yong Liang, Hao Li
  • Patent number: 7169619
    Abstract: High quality epitaxial layers of monocrystalline oxide materials (24) can be grown overlying monocrystalline substrates (22) such as large silicon wafers. The monocrystalline oxide layer (24) comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer serves as a decoupling layer between the substrate and the buffer layer so that the substrate and the buffer is crystal-graphically, chemically, and dielectrically decoupled. In addition, high quality epitaxial accommodating buffer layers may be formed overlying vicinal substrates using a low pressure, low temperature, alkaline-earth metal-rich process.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: January 30, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yong Liang, Ravindranath Droopad, Xiaoming Hu, Jun Wang, Yi Wei, Zhiyi Yu
  • Patent number: 7141857
    Abstract: Semiconductor structures and processes for fabricating semiconductor structures comprising hafnium oxide layers modified with lanthanum oxide or a lanthanide-series metal oxide are provided. A semiconductor structure in accordance with an embodiment of the invention comprises an amorphous layer of hafnium oxide overlying a substrate. A lanthanum-containing dopant or a lanthanide-series metal-containing dopant is comprised within the amorphous layer of hafnium oxide. The process comprises growing an amorphous layer of hafnium oxide overlying a substrate. The amorphous layer of hafnium oxide is doped with a dopant having the chemical formulation LnOx, where Ln is lanthanum, a lanthanide-series metal, or a combination thereof, and X is any number greater than zero. The doping step may be performed during or after growth of the amorphous layer of hafnium oxide.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 28, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhiyi Yu, Jay A. Curless, Yong Liang, Alexandra Navrotsky, Sergey Ushakov, Bich-Yen Nguyen, Alexander Demkov
  • Publication number: 20060216934
    Abstract: Methods for fabricating high work function p-MOS device metal electrodes are provided. In one embodiment, a method is provided for producing a metal electrode including the steps of: providing a high k dielectric stack with an exposed surface; contacting the exposed surface of the high k dielectric stack with a vapor of a metal oxide wherein the metal oxide is selected from the group consisting of RuOx, IrOx, ReOx, MoOx, WOx, VOx, and PdOx; and contacting the exposed surface of the dielectric stack with a vapor of an additive selected from the group consisting of SiO2, Al2O3, HfO2, ZrO2, MgO, SrO, BaO, Y2O3, La2O3, and TiO2, whereby contacting the exposed surface of the dielectric stack with the vapor of the metal oxide and the vapor of the additive forms an electrode and wherein the additive is present at an amount between about 1% to about 50% by atomic weight percent in the electrode.
    Type: Application
    Filed: March 28, 2005
    Publication date: September 28, 2006
    Inventors: Yong Liang, Clarence Tracy
  • Patent number: 7109740
    Abstract: A method for re-testing semiconductor device includes following processes: (1) providing a first carrier for accommodating semiconductor devices which have been tested; (2) taking the semiconductor devices out from the first carrier and placing them according to the information of a fist map by a pick-and-place machine, wherein the information of the first map has the coordinates of the positions of the film frame where the semiconductor is to be placed; (3) placing the film frame with the semiconductor devices placed thereon to a testing machine, and re-testing the semiconductor devices according to the information of the first map by the tester; (4) placing the film frame with the semiconductor devices attached thereon to a pick-and-place machine, and taking the semiconductor devices out according to the result of the retesting from the film frame, and placing the semiconductor devices on at least one carriers.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: September 19, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chin-Chen Chuan, Chiu-Cheng Lin, Cheng Chieh Lee, Kuei Lin Huang, Yong Liang Chen, Jui Liang Wang, Pao Ta Chien, Hsiang-Han Kung, Chao Hsiung Hwu
  • Publication number: 20060197227
    Abstract: Semiconductor structures, and methods for fabricating semiconductor structures, comprising high dielectric constant stacked structures are provided. A stacked dielectric structure (16) in accordance with one exemplary embodiment of the present invention has a first amorphous dielectric layer (18) comprising HfXZr1-XO2, where 0?X?1. An amorphous interlayer (20) overlies the first amorphous dielectric layer. The interlayer has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO4. A second amorphous dielectric layer (22) overlies the interlayer. The second amorphous dielectric layer comprises HfYZr1-YO2, where 0?Y?1. The stacked dielectric structure (16) has a net dielectric constant that is approximately no less than the dielectric constant of HfZrO4.
    Type: Application
    Filed: February 24, 2005
    Publication date: September 7, 2006
    Inventors: Yong Liang, Hao Li
  • Patent number: 7094675
    Abstract: A method for producing quantum dots. The method includes cleaning an oxide substrate and separately cleaning a metal source. The substrate is then heated and exposed to the source in an oxygen environment. This causes metal oxide quantum dots to form on the surface of the substrate.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: August 22, 2006
    Assignee: Battelle Memorial Institute
    Inventors: Yong Liang, John L. Daschbach, Yali Su, Scott A. Chambers
  • Patent number: 7034202
    Abstract: The invention provides methods and compositions for heavy metal phytoremediation, including plants which are genetically engineered to overexpress glutamylcysteine synthetase (ECS) and thereby provide enhanced heavy metal accumulation. In various embodiments, the plants comprise a gene encoding ECS operably linked to a heterologous promoter, the plant is a member of the Brassicaceae family. In general, the methods comprise the steps of growing such plants in a medium such as soil or water comprising a heavy metal, under conditions wherein ECS is overexpressed, whereby the plant provides enhanced accumulation of the heavy metal, whereby the heavy metal content of the medium is decreased.
    Type: Grant
    Filed: July 30, 1999
    Date of Patent: April 25, 2006
    Assignee: The Regents of the University of California
    Inventors: Norman Terry, Elizabeth Pilon-Smits, Yong Liang Zhu
  • Publication number: 20060003602
    Abstract: Semiconductor structures and processes for fabricating semiconductor structures comprising hafnium oxide layers modified with lanthanum oxide or a lanthanide-series metal oxide are provided. A semiconductor structure in accordance with an embodiment of the invention comprises an amorphous layer of hafnium oxide overlying a substrate. A lanthanum-containing dopant or a lanthanide-series metal-containing dopant is comprised within the amorphous layer of hafnium oxide. The process comprises growing an amorphous layer of hafnium oxide overlying a substrate. The amorphous layer of hafnium oxide is doped with a dopant having the chemical formulation LnOx, where Ln is lanthanum, a lanthanide-series metal, or a combination thereof, and X is any number greater than zero. The doping step may be performed during or after growth of the amorphous layer of hafnium oxide.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Zhiyi Yu, Jay Curless, Yong Liang
  • Publication number: 20050287285
    Abstract: The invention is based, in part, on the discovery that the addition of cations, such as calcium or magnesium ions, to muscle tissue before solubilization of the muscle proteins enhances removal of membranes, which reduces oxidation and spoilage of the muscle tissue.
    Type: Application
    Filed: April 11, 2003
    Publication date: December 29, 2005
    Inventors: Herbert Hultin, Yong Liang
  • Patent number: 6916717
    Abstract: High quality monocrystalline metal oxide layers are grown on a monocrystalline substrate such as a silicon wafer. The monocrystalline metal oxide is grown on the silicon substrate at a temperature low enough to prevent deleterious and simultaneous oxidation of the silicon substrate. After a layer of 1-3 monolayers of the monocrystalline oxide is grown, the growth is stopped and the crystal quality of that layer is improved by a higher temperature anneal. Following the anneal, the thickness of the layer can be increased by restarting the low temperature growth. An amorphous silicon oxide layer can be grown at the interface between the monocrystalline metal oxide layer and the silicon substrate after the thickness of the monocrystalline oxide reaches a few monolayers.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: July 12, 2005
    Assignee: Motorola, Inc.
    Inventors: Hao Li, Ravindranath Droopad, Daniel S. Marshall, Yi Wei, Xiao M. Hu, Yong Liang
  • Patent number: 6890816
    Abstract: High quality epitaxial layers of monocrystalline perovskite materials (18) can be grown overlying monocrystalline substrates (12) such as gallium arsenide wafers by forming a metal template layer (16) on the monocrystalline substrate. The structure includes a metal-containing layer (16) to mitigate unwanted oxidation of underlying layers and a low-temperature seed layer (19) that prevents degradation of an epitaxial layer (14) during growth of the perovskite layer (18).
    Type: Grant
    Filed: February 7, 2003
    Date of Patent: May 10, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yong Liang, Ravindranath Droopad
  • Patent number: 6885065
    Abstract: A ferromagnetic semiconductor structure is provided. The structure includes a monocrystalline semiconductor substrate and a doped titanium oxide anatase layer overlying the semiconductor substrate.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: April 26, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yong Liang, Ravindranath Droopad, Hao Li, Zhiyi Yu
  • Patent number: 6852588
    Abstract: Methods are provided for fabricating semiconductor structures and semiconductor device structures utilizing epitaxial Hf3Si2 layers. A process in accordance with one embodiment of the invention begins by disposing a silicon substrate in a processing chamber. The pressure within the processing chamber and a temperature of the silicon substrate in the range of approximately 250° C. to approximately 700° C. is established. A layer of Hf3Si2 then is grown overlying the silicon substrate at a rate in the range of about one (1) to about five (5) monolayers per minute.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: February 8, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Zhiyi Yu, Jay A. Curless, Yong Liang