Abstract: Systems, methods, and devices for relieving overpressure associated with thermal expansion of fluid within a closed cavity of a subsea manifold assembly. The subsea manifold assembly may comprise a header bore fluidly connected to one or more branch connections. A unidirectional valve is included at the branch connections to allow fluid leakage from the closed cavity into a header bore of the subsea manifold assembly to thereby reduce a pressure within the cavity while in the closed position.

Abstract: The present invention relates to a system and a method for encoding/decoding 2D data for 3D rendering, and an apparatus therefor. A method for encoding 2D video data for 3D rendering according to one aspect of the present disclosure may include: generating one or more 2D patch data from 2D data; generating patch area separation information for distinguishing the 2D patch data in the 2D data; generating 3D spatial information for the 2D data and/or the 2D patch data; generating a video stream including the 2D data and/or the 2D patch data and metadata for the video stream, wherein the metadata includes the patch area separation information and the 3D spatial information; and encoding the video stream and the metadata.

Abstract: The present invention relates to a system and a method for encoding/decoding 3D data, and an apparatus therefor. A method for encoding 3D data according to one aspect of the present disclosure may include: generating 2D patch data from 2D data; generating patch area separation information for distinguishing the 2D patch data in the 2D data; generating 3D spatial information for the 2D data and/or the 2D patch data; converting the 2D data and/or the 2D patch data into 3D data based on the patch area separation information and the 3D spatial information; and encoding the 3D data.

Abstract: There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including first select transistors, memory cells, and second select transistors, which are connected between bit lines and a source line; a precharge controller for monitoring a program operation of the memory cells, and changing a precharge mode of unselected strings among strings included in the memory block according to a monitoring result; and a select line voltage generator for generating a positive voltage or a negative voltage, which is applied to a second select line connected to the second select transistors, according to the precharge mode selected in the precharge controller.

Abstract: Systems, methods, and devices for relieving overpressure associated with thermal expansion of fluid within a closed cavity of a subsea manifold assembly. The subsea manifold assembly may comprise a header bore fluidly connected to one or more branch connections. A unidirectional valve is included at the branch connections to allow fluid leakage from the closed cavity into a header bore of the subsea manifold assembly to thereby reduce a pressure within the cavity while in the closed position.

Abstract: A micromanipulator comprising: a first frame portion defining an axial direction extending from a first proximal end to a first distal end; a second frame portion; a tool holder coupled to the second frame portion; a first connecting portion coupling the second frame portion and the first frame portion at the first distal end in resilient pivotable coupling; and a second connecting portion coupling the second frame portion and the first frame portion at the first proximal end in resilient pivotable coupling. The first frame portion, the second frame portion, the first connecting portion, and a second connecting portion form a flexural frame. The flexural frame is resiliently biased to a first frame state in which the tool holder is in a retracted position.

Abstract: Embodiments of the present disclosure provide a method for setting, by a computing device, a bias voltage of a driver integrated circuit that supplies voltage to a display panel. The method includes: selecting one of a plurality of pre-stored scenarios based on a change in a flicker index and applying a bias voltage to the display panel according to a level based on the selected scenario, and recording, to the driver integrated circuit, a level of the bias voltage which corresponds to a minimum value in a fitted quadratic function. According to a system and a method for setting the bias voltage according to embodiments of the present disclosure, the level of the bias voltage that minimizes the flicker phenomenon by minimizing a change in luminance of the display panel based on the bias voltage can be calculated through minimal measurements.

Abstract: A method and a device for transmitting and obtaining dynamic 3-dimensional (3D) avatar data are provided. The method for transmitting dynamic 3D avatar data may include generating a plurality of data elements configuring the dynamic 3D avatar data; performing first encoding and transmission for a first data element of the plurality of data elements; and performing second encoding and transmission for a second data element of the plurality of data elements. Each of at least one of the first data element or the second data element may be divided into a plurality of sub-data elements.

Abstract: An analog-to-digital converter is provided. An analog-to-digital converter includes a comparator including a first input node receiving an output of a plurality of first unit capacitors and a second input node receiving an output of a plurality of second unit capacitors, a control logic configured to output first and second control signals on the basis of an output signal of the comparator, and a reference voltage adjustment circuit configured to adjust an output voltage provided to the comparator on the basis of the first and second control signals. The reference voltage adjustment circuit comprises a first pull-up circuit configured to apply a first reference voltage to each of the plurality of first unit capacitors and a first pull-down circuit configured to apply a second reference voltage to each of the plurality of second unit capacitors, based on v.

Abstract: Disclosed are a structure, including a junction field effect transistor (JFET), and a method of forming the structure. The JFET includes a channel region and source and drain regions above the channel region. The JFET also includes a first gate region below the channel region and a second gate region above the channel region positioned laterally between and isolated from the source and drain regions. The first gate region underlies the drain region and is offset from the source region and at least that portion of the second gate region adjacent to the source region. Specifically, the first gate region is either completely offset from both the source region and the second gate region or is completely offset from the source region and only partially underlies the second gate region. In the JFET, resistance on is reduced and saturation drain current is increased without significantly impacting breakdown or pinch-off voltages.

Abstract: An amplifier includes a first stage amplifier circuit configured to receive an input voltage and a first multi-stage amplifier circuit and a second multi-stage amplifier circuit branching off from an output terminal of the first stage amplifier circuit and each including a second stage and a third stage. Each of the first multi-stage amplifier circuit and the second multi-stage amplifier circuit may be configured to sample a voltage corresponding to a first bias current corresponding to the second stage and a voltage corresponding to a second bias current corresponding to the third stage in a first phase, and bias the second stage with the voltage corresponding to the first bias current and bias the third stage with the voltage corresponding to the second bias current in a second phase.

Abstract: A method of encoding a dynamic mesh includes creating a base mesh through mesh decimation, subdividing the base mesh, extracting displacement information for the subdivided mesh, and encoding the base mesh and the displacement information. In this instance, mesh subdivision information for subdivision of the base mesh is encoded and signaled.

Abstract: A display device according to one embodiment includes a data drive unit that converts image data into a data signal and outputs the data signal, a multiplexer unit that time-divides the data signal output from the data drive unit and outputs the time-divided data signals, and a gate drive unit that outputs a gate signal synchronized with the data signal to a first gate line, a second gate line, a third gate line, and a fourth gate line, wherein the multiplexer unit includes a first multiplexer and a second multiplexer, when the gate signal is sequentially input to the first gate line and the second gate line, the first multiplexer and the second multiplexer are sequentially turned on, and when the gate signal is sequentially input to the third gate line and the fourth gate line, the second multiplexer and the first multiplexer are sequentially turned on.

Abstract: An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gated body transistors and methods of manufacture. The structure includes: at least one fin structure composed of semiconductor material and including a channel region between a source region and a drain region; and a gated body under the channel region of the at least one fin structure.

Abstract: An overlay measurement device includes a light source configured to direct an illumination to an overlay measurement target in which a first overlay key in a first layer and a second overlay key in a second layer are positioned, the second layer being stacked on an upper portion or a lower portion of the first layer, a lens assembly including an objective lens configured to condense the illumination on a measurement position of at least one point in the overlay measurement target and a lens focus actuator configured to control a distance between the objective lens and the overlay measurement target, and a detector configured to acquire a focus image at the measurement position based on a beam reflected on the measurement position.

Abstract: A substrate processing apparatus including the controller are provided. The controller includes: a signal analyzer configured to detect at least one of an amplitude, phase, and frequency of a first signal, which is provided to a chamber; a radio frequency (RF) signal generator configured to generate an RF signal with a natural frequency based on a power of the first signal; a harmonic controller configured to generate a second signal based on the power of the first signal and at least one of the amplitude, phase, and frequency of the first signal, the second signal having a different amplitude, a different phase, and/or a different frequency from the RF signal; an operator configured to perform an operation on the RF signal and the second signal; and a filter configured to generate an RF control signal by filtering an output signal of the operator.

Abstract: A fast recovery diode includes a substrate; an epitaxial layer formed on the substrate; a P-type low-concentration doping region formed in an upper portion of the epitaxial layer and a P-type high-concentration doping region formed on the P-type low-concentration doping region; a P-type guard ring formed in the upper portion of the epitaxial layer to surround the P-type low-concentration doping region and P-type high-concentration doping region; a field oxide layer formed on the P-type guard ring and the P-type high-concentration doping region; an anode electrode formed to overlap the P-type high-concentration doping region and a portion of the field oxide layer; and a cathode electrode formed below the substrate.

Abstract: A memory device includes a memory block, peripheral circuit, and control logic. The memory block includes a plurality of pages coupled to a plurality of word lines, respectively. The peripheral circuit is configured to perform a program loop including a program pulse operation of applying a program voltage to a selected word line, and a verify operation of applying at least one verify voltage corresponding to the program voltage to the selected word line and applying a verify pass voltage to unselected word lines. The control logic is configured to increase a level of the verify pass voltage applied to at least one unselected word line among the unselected word lines whenever the peripheral circuit performs the next program loop when threshold voltages of memory cells included in a page coupled to the selected word line are greater than a reference level.