Abstract: A photodiode device may include a semiconductor substrate, a multiplication layer disposed in the semiconductor substrate and having a first width, a dielectric layer disposed over the multiplication layer, a charge layer coupled to the multiplication layer and having a second width, and an absorption layer disposed over the charge layer and having a third width. The second width of the charge layer may be smaller than the first width of the multiplication layer, and the third width of the absorption layer may be greater than the second width of the charge layer.

Abstract: A memory device includes a memory block, peripheral circuit, and control logic. The memory block includes a plurality of pages coupled to a plurality of word lines, respectively. The peripheral circuit is configured to perform a program loop including a program pulse operation of applying a program voltage to a selected word line, and a verify operation of applying at least one verify voltage corresponding to the program voltage to the selected word line and applying a verify pass voltage to unselected word lines. The control logic is configured to increase a level of the verify pass voltage applied to at least one unselected word line among the unselected word lines whenever the peripheral circuit performs the next program loop when threshold voltages of memory cells included in a page coupled to the selected word line are greater than a reference level.

Abstract: A method of an IAB node may comprise: receiving an RRC message including measurement control information from a base station; transmitting RRC reconfiguration information including the measurement control information to each of a plurality of terminals; receiving a measurement report message including a measurement report generated by each of the plurality of terminals based on the measurement control information from each of the plurality of terminals; and grouping the measurement report messages received from the plurality of terminals into a grouped message report message, and transmitting the grouped measurement report message to the base station according to a grouped measurement reporting periodicity.

Abstract: Structures for an avalanche photodetector and methods of forming a structure for an avalanche photodetector. The structure comprises a substrate having a first conductivity type, a first semiconductor layer that defines an absorption region of the avalanche photodetector, a dielectric layer between the first semiconductor layer and the substrate, a charge control region comprising a semiconductor material having a second conductivity type opposite to the first conductivity type and a different bandgap from the first semiconductor layer, and a second semiconductor layer that extends through the dielectric layer from the charge control region to the substrate. The second semiconductor layer defines a multiplication region of the avalanche photodetector.

Abstract: A method of a terminal, according to an exemplary embodiment of the present disclosure, may include: requesting access to a mobile integrated access backhaul (IAB) based on cell search; receiving a tracking area (TA) update procedure stop request message from an Access and Mobility Management Function (AMF) of a core network; and deactivating a TA update procedure based on the TA update procedure stop request message.

Abstract: A method of an integrated access and backhaul (IAB) node may include: receiving, from a target base station, one or more user equipment (UE) context setup request messages including terminal radio resource reconfiguration information; sharing context information including the terminal radio resource reconfiguration information with a source IAB-distributed unit 1 (IAB-DU1); configuring terminal reconfiguration information using the shared context information; and transmitting one or more UE context setup response messages including the terminal reconfiguration information to the target base station in response to the one or more UE context setup request messages.

Abstract: An analog-to-digital converting circuit for converting an analog signal into a digital signal includes a plurality of reference voltage generators each generating a reference voltage, a plurality of reference voltage decoupling capacitors respectively corresponding to the reference voltage generators, and an analog-to-digital converter generating a comparison voltage based on the reference voltage and generating the digital signal corresponding to the analog signal based on a result of comparing the comparison voltage with the analog signal. At least one different combination of the reference voltage generators and the reference voltage decoupling capacitors is connected to the analog-to-digital converter in each of a plurality of conversion periods.

Abstract: A method of an aerial vehicle for urban air mobility may include: reporting, to a first base station, a measurement result for neighboring base stations including a second base station; receiving, from the first base station and as a processing result based on the measurement result, an indication of a failure of a handover to the second base station; requesting, to a control station, first location information indicating a first location to move according to the failure of the handover; receiving the first location information from the control station; and moving according to the received first location information.

Abstract: The present invention relates to a method and apparatus for encoding a displacement video using image tiling. A method for encoding multi-dimensional data according to an embodiment of the present disclosure may comprise: converting the multi-dimensional data into one or more frames with two-dimensional characteristics; generating one or more frame groups by grouping the one or more frames with pre-configured number units; reconstructing frames belonging to each frame group into a tiled frame; and generating a bitstream by encoding the tiled frame. Here, the tiled frame may be constructed with one or more blocks, and each block may be constructed by rearranging pixels existing at the same location in the frames.

Abstract: There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including first select transistors, memory cells, and second select transistors, which are connected between bit lines and a source line; a precharge controller for monitoring a program operation of the memory cells, and changing a precharge mode of unselected strings among strings included in the memory block according to a monitoring result; and a select line voltage generator for generating a positive voltage or a negative voltage, which is applied to a second select line connected to the second select transistors, according to the precharge mode selected in the precharge controller.

Abstract: A memory device includes a memory block, a peripheral circuit, and control logic. The memory block includes memory cells. The peripheral circuit performs a program operation including a plurality of program loops. Each of the plurality of program loops includes a program pulse application operation and a verify operation. The control logic controls the peripheral circuit to store cell status information and apply a program limit voltage. The control logic sets a verify pass reference and applies the program limit voltage determined based on the cell status information.

Abstract: A structure includes a photodetector including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other in a stack. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate on a second region separated from the first region by a trench isolation. The photodetector is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

Abstract: An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.

Abstract: The present disclosure provides a technology for a level shifter that allows the selection of a single-stage level shifter or a two-stage level shifter by a simple alteration to wiring. When the single-stage level shifter is selected, some circuits may remain as dummy circuits.

Abstract: A hybrid low drop-out (LDO) regulator is provided. The hybrid LDO regulator provides current to a load block, and includes: an analog LDO regulator configured to provide a first current corresponding to an average current consumed by the load block; and a digital LDO regulator configured to provide a second current corresponding to a peak current consumed by the load block based on information indicating the peak current is consumed.

Abstract: An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

Abstract: An amplifier and an electronic system including the same are provided. An amplifier includes a first NMOS transistor configured to receive a first input, a second NMOS transistor configured to receive a second input, the second NMOS transistor including a source connected to a source of the first NMOS transistor, a first resistor including a first end connected to a drain of the first NMOS transistor and a second end connected to a first output, a second resistor including a first end connected to a drain of the second NMOS transistor, and a second end connected to a second output, and the amplifier is configured to generate the first output and the second output based on the first input, the second input, a resistance value of the first resistor, and a resistance value of the second resistor.

Abstract: A low dropout (LDO) regulator includes an operational amplifier connected to a capacitor receiving an input voltage through a first end and storing an offset voltage through a second end, a first transistor configured to control an electrical connection between the input voltage and the first end of the operational amplifier, a second transistor configured to control an electrical connection between the first end of the operational amplifier and a first node, a third transistor configured to control an electrical connection between an output end of the operational amplifier and a second node, and a fourth transistor configured to control an electrical connection between a second end of the operational amplifier and the output end of the operational amplifier.

Abstract: An operation method of a terminal in a communication system may comprise: in response to occurrence of uplink (UL) data, transmitting a scheduling request (SR) for the UL data to a base station; performing a UL timing alignment procedure with the base station when a UL timing between the terminal and the base station is not synchronized; receiving a UL grant for the UL data from the base station; and transmitting the UL data to the base station using resources indicated by the UL grant.

Abstract: Disclosed herein is a method of creating an image stitching workflow including acquiring 360-degree virtual reality (VR) image parameters necessary to makes a request for image stitching and create the image stitching workflow, acquiring a list of functions applicable to the image stitching workflow, creating the image stitching workflow based on functions selected from the list of functions, determining the number of media processing entities necessary to perform tasks configuring the image stitching workflow and generating a plurality of media processing entities according to the determined number of media processing entities, and allocating the tasks configuring the image stitching workflow to the plurality of media processing entities.