Patents by Inventor Yong Lu

Yong Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220123352
    Abstract: A high-temperature stable solid-state bipolar battery is provided. The battery includes two or more electrodes, one or more solid-state electrolyte layers, and an ionogel disposed within void spaces within the battery. Each electrode includes a plurality of solid-state electroactive particles. Each solid-state electrolyte layer includes a plurality of solid-state electrolyte particles and a first solid-state electrolyte layer of the one or more solid-state electrolyte layers may be disposed between a first electrode and a second electrode of the two or more electrodes. The ionogel is disposed within void spaces between the two or more electrodes, the solid-state electroactive particles of the two or more electrodes, the solid-state electrolyte particles of the one or more solid-state electrolyte layers, and the one or more solid-state electrolyte layers, such that the battery has an reduced interparticle porosity. The ionogel may have an ionic conductivity between about 0.1 mS/Cm and about 10 mS/cm.
    Type: Application
    Filed: September 21, 2021
    Publication date: April 21, 2022
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Zhe LI, Yong LU, Qili SU, Meiyuan WU, Haijing LIU
  • Patent number: 11298684
    Abstract: A catalyst for oxidative coupling of methane, and preparation and application thereof. The catalyst comprises: a manganese sesquioxide, a tungstate, a manganese composite oxide having a perovskite structure and/or a spinel structure, and a carrier. The manganese sesquioxide, tungstate, and manganese composite oxide having a perovskite structure and/or a spinel structure are supported on the carrier, or the manganese sesquioxide and tungstate are supported on the admixture of the said manganese composite oxide having a perovskite structure and/or a spinel structure and the said carrier. Based on 100 parts by weight of the catalyst, the content of the manganese sesquioxide is a parts by weight, the content of the tungstate is b parts by weight, the content of the manganese composite oxide having the perovskite structure and/or the spinel structure is c parts by weight The content of the carrier is d parts by weight. 0<a?20, 1?b?20, 1?c?40, 20?d<98.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: April 12, 2022
    Assignees: EAST CHINA NORMAL UNIVERSITY, ZHEJIANG JIRUITONG NEW MATERIAL CO., LTD.
    Inventors: Yong Lu, Xin Zhang, Pengwei Wang, Guofeng Zhao, Ye Liu, Mingyuan He
  • Publication number: 20220059539
    Abstract: A method for preparing a semiconductor structure includes: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming a first insulation layer, the first insulation layer at least covering an inner wall of the groove; forming a channel layer, the channel layer at least covering an inner wall of the first insulation layer; forming a second insulation layer, the second insulation layer at least covering an inner wall of the channel layer; filling the groove with a word line structure; removing part of the semiconductor substrate, part of the first insulation layer, and part of the channel layer, and forming a recess region in an outer side wall of the second insulation layer; and forming a source-drain in the recess region, the source-drain being electrically connected with the channel layer.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 24, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Gongyi WU, Yong LU, Longyang CHEN
  • Publication number: 20220052052
    Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate, a trench and a word line. The substrate includes an isolation structure and an active area. The active area includes irons of a first type. The trench is arranged in the active area, an inner surface of the trench includes an inversion doping layer and an oxide layer which are arranged adjacent to each other, and the inversion doping layer is arranged above the oxide layer. The word line is arranged in the trench. The inversion doping layer includes ions of a second type. The first type is contrary to the second type.
    Type: Application
    Filed: August 17, 2021
    Publication date: February 17, 2022
    Inventors: Gongyi WU, Yong Lu, Longyang Chen
  • Publication number: 20220051933
    Abstract: A semiconductor device manufacturing method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region; depositing at least two insulating layers on a surface of the semiconductor substrate, each of the insulating layer has a different etch rate under a same etching condition; and removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of an upper insulating layer, and keeping all the insulating layers in the grooves located over the word line structures.
    Type: Application
    Filed: September 9, 2021
    Publication date: February 17, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Gongyi WU, Yong LU, Youquan YU
  • Publication number: 20220037459
    Abstract: A capacitor structure and a method of manufacturing the same, and a memory are provided. The method includes the following operations. A substrate is provided. A first conductive structure with a shape of column is formed on the substrate. A second conductive structure is formed on the substrate. The second conductive structure surrounds the first conductive structure and is spaced with the first conductive structure. The first conductive structure and the second conductive structure together form a bottom electrode. A capacitor dielectric layer is formed. The capacitor dielectric layer covers the surface of the substrate and the surface of the bottom electrode. A top electrode covering the surface of the capacitor dielectric layer is formed.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 3, 2022
    Inventors: Yong LU, Gongyi WU, Hongkun SHEN
  • Publication number: 20220037460
    Abstract: The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.
    Type: Application
    Filed: October 18, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yong LU
  • Publication number: 20220037478
    Abstract: A buried wordline structure fabrication method includes: providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom; performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; and forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.
    Type: Application
    Filed: August 21, 2021
    Publication date: February 3, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Yong LU, Hongkun SHEN
  • Publication number: 20220013644
    Abstract: A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.
    Type: Application
    Filed: July 30, 2021
    Publication date: January 13, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Gongyi WU, Youquan YU, Yong LU
  • Publication number: 20220013655
    Abstract: A method for preparing a semiconductor device includes the following operations. A semiconductor substrate is provided, and a gate dielectric layer, a first conductive layer, and a support layer with a through hole are sequentially formed on the semiconductor substrate. A barrier layer and a second conductive layer are formed in the through hole. The support layer and a part of the first conductive layer located below the support layer are removed to form a primary gate pattern and expose the gate dielectric layer. A gate sidewall protective layer is formed on a sidewall of the primary gate pattern. An insulating layer is formed on a top of the primary gate pattern, a surface of the gate sidewall protective layer and a surface of the exposed part of the gate dielectric layer. A part of the insulating layer and a part of the gate dielectric layer are removed.
    Type: Application
    Filed: August 3, 2021
    Publication date: January 13, 2022
    Inventors: Gongyi WU, Yafei HUANG, Yong LU
  • Patent number: 11217826
    Abstract: A method of making the sulfide-impregnated solid-state battery is provided. The method comprises providing a cell core that is constructed by cell unit. The cell core is partially sealed into the packaging such as the Al laminated film and metal can. The method further comprises introducing a sulfide solid-state electrolyte (S-SSE) precursor solution in the cell core, the S-SSE precursor solution comprises a sulfide solid electrolyte and a solvent. The method further comprises evaporating the solvent from the cell core to dry the cell core to solidify the sulfide-based solid-state electrolyte within the cell core and pressurizing the cell core to densify the solid sulfide-base electrolyte within the cell core. The cell core is then fully sealed.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: January 4, 2022
    Assignee: GM Global Technology Operations LLC
    Inventors: Zhe Li, Xiaochao Que, Haijing Liu, Yong Lu, Mark W. Verbrugge, Meiyuan Wu
  • Publication number: 20210408006
    Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; forming sidewall dielectric layers on surfaces of the conductive structures, and then depositing sequentially and alternately to form at least two supporting layers and sacrificial layers; etching the supporting layers and the sacrificial layers to form contact holes exposing the surfaces of the conductive structures; and forming an electrode layer on surfaces of the contact holes.
    Type: Application
    Filed: September 8, 2021
    Publication date: December 30, 2021
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yong LU
  • Publication number: 20210406686
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for balanced-weight sparse convolution processing. An exemplary method comprises: obtaining an input tensor and a plurality of filters at a layer within a neural network; segmenting the input tensor into a plurality of sub-tensors; dividing a channel dimension of each of the plurality of filters into a plurality of channel groups; pruning each of the plurality of filters so that each of the plurality of channel groups of each filter comprises a same number of non-zero weights; segmenting each of the plurality of filters into a plurality of the sub-filters according to the plurality of channel groups; and assigning the plurality of sub-tensors and the plurality of sub-filters to a plurality of processors for parallel convolution processing.
    Type: Application
    Filed: August 2, 2021
    Publication date: December 30, 2021
    Inventors: ZHIBIN XIAO, ENXU YAN, WEI WANG, YONG LU
  • Publication number: 20210343833
    Abstract: A double-sided capacitor structure and a method for forming the same are provided. The method includes: providing a base including a substrate, capacitor contacts in the substrate, a stacked structure on a surface of the substrate, and capacitor holes penetrating through the stacked structure and exposing the capacitor contacts, and the stacked structure includes sacrificial layers and supporting layers which are alternately stacked in a direction perpendicular to the substrate; forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; filling the capacitor holes with a first conductive material to form a first conductive filling layer; completely removing several of the sacrificial layers and/or the supporting layers to remain at least two of the supporting layers; and forming a second dielectric layer and a third electrode layer that covers a surface of the second dielectric layer.
    Type: Application
    Filed: July 13, 2021
    Publication date: November 4, 2021
    Inventor: Yong LU
  • Publication number: 20210335993
    Abstract: A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes: a stacked structure is formed on a surface of a substrate, the stacked structure including supporting layers and sacrificial layers which are alternately stacked; a buffer layer is formed on a surface of the stacked structure facing away from the substrate; capacitor holes penetrating through the stacked structure and the buffer layer and exposing capacitor contacts are formed; a first electrode layer covering inner walls of the capacitor holes is formed; an etching window penetrating through the buffer layer is formed; part of the supporting layers and all of the sacrificial layers in the stacked structure are removed along the etching window; the buffer layer is removed; and a dielectric layer and a second electrode layer are formed to form a capacitor.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 28, 2021
    Inventor: Yong LU
  • Patent number: 11145922
    Abstract: A solid-state battery cell having a capacitor interlayer is disclosed. The solid-state battery includes an anode, a cathode spaced from the anode, a solid-state electrolyte layer disposed between the anode and the cathode, and a capacitor assisted interlayer sandwiched between at least one of (i) the anode and solid-state electrolyte layer, and (ii) the cathode and the solid-state electrolyte layer. The capacitor assisted interlayer comprise at least one of a polymer-based material, an inorganic material, and a polymer-inorganic hybrid material; and a capacitor anode active material or a capacitor cathode active material. The polymer-based material includes at least one of a poly(ethylene glycol) methylether acrylate with Al2O3 and LiTFSI, a polyethylene oxide (PEO) with LiTFSI, and a poly(vinylidene fluoride) copolymer with hexafluoropropylene (PVDF-HFP)-based gel electrolyte. The inorganic material includes a 70% Li2S-29% P2S5-1% P2O5.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: October 12, 2021
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Zhe Li, Xiaochao Que, Haijing Liu, Qili Su, Yong Lu
  • Patent number: 11144823
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for hierarchical weight-sparse convolution processing are described. An exemplary method comprises: obtaining an input tensor and a filter at a convolution layer of a neural network; segmenting the filter into a plurality of sub-filters; generating a hierarchical bit representation of the filter representing a plurality of non-zero weights in the filter, wherein the hierarchical bit representation comprises a first layer, the first layer comprising a plurality of bits respectively corresponding to the plurality of sub-filters in the filter, each of the plurality of bits indicating whether the corresponding sub-filter includes at least one non-zero weight; and performing multiply-and-accumulate (MAC) operations based on the hierarchical bit representation of the filter and the input tensor.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: October 12, 2021
    Assignee: MOFFETT TECHNOLOGIES CO., LIMITED
    Inventors: Zhibin Xiao, Enxu Yan, Wei Wang, Yong Lu
  • Patent number: 11113601
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for balanced-weight sparse convolution processing.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 7, 2021
    Assignee: MOFFETT TECHNOLOGIES CO., LIMITED
    Inventors: Zhibin Xiao, Enxu Yan, Wei Wang, Yong Lu
  • Patent number: 11068397
    Abstract: Disclosed aspects relate to accelerator sharing among a plurality of processors through a plurality of coherent proxies. The cache lines in a cache associated with the accelerator are allocated to one of the plurality of coherent proxies. In a cache directory for the cache lines used by the accelerator, the status of the cache lines and the identification information of the coherent proxies to which the cache lines are allocated are provided. Each coherent proxy maintains a shadow directory of the cache directory for the cache lines allocated to it. In response to receiving an operation request, a coherent proxy corresponding to the request is determined. The accelerator communicates with the determined coherent proxy for the request.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Peng Fei BG Gou, Yang Liu, Yang Fan EL Liu, Yong Lu
  • Patent number: 11022317
    Abstract: A movable burner of a gas cooktop includes a rotating shaft, a linear motion mechanism configured to perform a linear motion, a burner head, and a limit unit configured to limit a stroke range of the linear motion mechanism. The burner head includes a plurality of brackets having a plurality of gas outlets for gas to flow out and form a flame. Each bracket is separately hinged to the rotating shaft and separately connected to the linear motion mechanism such as to execute a rotation about the rotating shaft between at least two working positions, when driven by the linear motion mechanism, with the burner head having a flat upper surface in one of the two working positions, and with the burner head having a concave configuration in the other one of the two working positions.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 1, 2021
    Assignee: BSH Hausgeräte GmbH
    Inventors: Yong Lu, Junhui Xing, Qingsong Xie, Xiaofeng Yin