Abstract: The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.

Abstract: A buried wordline structure fabrication method includes: providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom; performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; and forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.

Abstract: A method for preparing a semiconductor device includes the following operations. A semiconductor substrate is provided, and a gate dielectric layer, a first conductive layer, and a support layer with a through hole are sequentially formed on the semiconductor substrate. A barrier layer and a second conductive layer are formed in the through hole. The support layer and a part of the first conductive layer located below the support layer are removed to form a primary gate pattern and expose the gate dielectric layer. A gate sidewall protective layer is formed on a sidewall of the primary gate pattern. An insulating layer is formed on a top of the primary gate pattern, a surface of the gate sidewall protective layer and a surface of the exposed part of the gate dielectric layer. A part of the insulating layer and a part of the gate dielectric layer are removed.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.

Abstract: A method of making the sulfide-impregnated solid-state battery is provided. The method comprises providing a cell core that is constructed by cell unit. The cell core is partially sealed into the packaging such as the Al laminated film and metal can. The method further comprises introducing a sulfide solid-state electrolyte (S-SSE) precursor solution in the cell core, the S-SSE precursor solution comprises a sulfide solid electrolyte and a solvent. The method further comprises evaporating the solvent from the cell core to dry the cell core to solidify the sulfide-based solid-state electrolyte within the cell core and pressurizing the cell core to densify the solid sulfide-base electrolyte within the cell core. The cell core is then fully sealed.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for balanced-weight sparse convolution processing. An exemplary method comprises: obtaining an input tensor and a plurality of filters at a layer within a neural network; segmenting the input tensor into a plurality of sub-tensors; dividing a channel dimension of each of the plurality of filters into a plurality of channel groups; pruning each of the plurality of filters so that each of the plurality of channel groups of each filter comprises a same number of non-zero weights; segmenting each of the plurality of filters into a plurality of the sub-filters according to the plurality of channel groups; and assigning the plurality of sub-tensors and the plurality of sub-filters to a plurality of processors for parallel convolution processing.

Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and provides a semiconductor structure and a forming method thereof. The forming method includes: providing a semiconductor substrate, where a surface of the semiconductor substrate is provided with a plurality of conductive structures arranged at intervals; forming sidewall dielectric layers on surfaces of the conductive structures, and then depositing sequentially and alternately to form at least two supporting layers and sacrificial layers; etching the supporting layers and the sacrificial layers to form contact holes exposing the surfaces of the conductive structures; and forming an electrode layer on surfaces of the contact holes.

Abstract: A double-sided capacitor structure and a method for forming the same are provided. The method includes: providing a base including a substrate, capacitor contacts in the substrate, a stacked structure on a surface of the substrate, and capacitor holes penetrating through the stacked structure and exposing the capacitor contacts, and the stacked structure includes sacrificial layers and supporting layers which are alternately stacked in a direction perpendicular to the substrate; forming a first electrode layer, a first dielectric layer and a second electrode layer on inner walls of the capacitor holes; filling the capacitor holes with a first conductive material to form a first conductive filling layer; completely removing several of the sacrificial layers and/or the supporting layers to remain at least two of the supporting layers; and forming a second dielectric layer and a third electrode layer that covers a surface of the second dielectric layer.

Abstract: A method for forming a semiconductor structure and a semiconductor structure are provided. The method includes: a stacked structure is formed on a surface of a substrate, the stacked structure including supporting layers and sacrificial layers which are alternately stacked; a buffer layer is formed on a surface of the stacked structure facing away from the substrate; capacitor holes penetrating through the stacked structure and the buffer layer and exposing capacitor contacts are formed; a first electrode layer covering inner walls of the capacitor holes is formed; an etching window penetrating through the buffer layer is formed; part of the supporting layers and all of the sacrificial layers in the stacked structure are removed along the etching window; the buffer layer is removed; and a dielectric layer and a second electrode layer are formed to form a capacitor.

Abstract: A solid-state battery cell having a capacitor interlayer is disclosed. The solid-state battery includes an anode, a cathode spaced from the anode, a solid-state electrolyte layer disposed between the anode and the cathode, and a capacitor assisted interlayer sandwiched between at least one of (i) the anode and solid-state electrolyte layer, and (ii) the cathode and the solid-state electrolyte layer. The capacitor assisted interlayer comprise at least one of a polymer-based material, an inorganic material, and a polymer-inorganic hybrid material; and a capacitor anode active material or a capacitor cathode active material. The polymer-based material includes at least one of a poly(ethylene glycol) methylether acrylate with Al2O3 and LiTFSI, a polyethylene oxide (PEO) with LiTFSI, and a poly(vinylidene fluoride) copolymer with hexafluoropropylene (PVDF-HFP)-based gel electrolyte. The inorganic material includes a 70% Li2S-29% P2S5-1% P2O5.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for hierarchical weight-sparse convolution processing are described. An exemplary method comprises: obtaining an input tensor and a filter at a convolution layer of a neural network; segmenting the filter into a plurality of sub-filters; generating a hierarchical bit representation of the filter representing a plurality of non-zero weights in the filter, wherein the hierarchical bit representation comprises a first layer, the first layer comprising a plurality of bits respectively corresponding to the plurality of sub-filters in the filter, each of the plurality of bits indicating whether the corresponding sub-filter includes at least one non-zero weight; and performing multiply-and-accumulate (MAC) operations based on the hierarchical bit representation of the filter and the input tensor.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for balanced-weight sparse convolution processing.

Abstract: Disclosed aspects relate to accelerator sharing among a plurality of processors through a plurality of coherent proxies. The cache lines in a cache associated with the accelerator are allocated to one of the plurality of coherent proxies. In a cache directory for the cache lines used by the accelerator, the status of the cache lines and the identification information of the coherent proxies to which the cache lines are allocated are provided. Each coherent proxy maintains a shadow directory of the cache directory for the cache lines allocated to it. In response to receiving an operation request, a coherent proxy corresponding to the request is determined. The accelerator communicates with the determined coherent proxy for the request.

Abstract: A movable burner of a gas cooktop includes a rotating shaft, a linear motion mechanism configured to perform a linear motion, a burner head, and a limit unit configured to limit a stroke range of the linear motion mechanism. The burner head includes a plurality of brackets having a plurality of gas outlets for gas to flow out and form a flame. Each bracket is separately hinged to the rotating shaft and separately connected to the linear motion mechanism such as to execute a rotation about the rotating shaft between at least two working positions, when driven by the linear motion mechanism, with the burner head having a flat upper surface in one of the two working positions, and with the burner head having a concave configuration in the other one of the two working positions.

Abstract: Example array substrates are provided. One example array substrate includes an underlying substrate, an antenna and a component layer, where the antenna and the component layer are located on a same side of the underlying substrate, where the component layer and the antenna are disposed at intervals, where the component layer includes a plurality of metal laminates and a plurality of dielectric laminates that are stacked, and where the plurality of metal laminates and the plurality of dielectric laminates are alternately disposed to form a plurality of thin film transistors.

Abstract: The present invention provides methods and compositions for Th9-cell mediated cancer therapy.

Abstract: The present disclosure relates to solid-state electrolytes and methods of making the same. The method includes admixing a sulfate precursor including one or more of Li2SO4 and Li2SO4.H2O with one or more carbonaceous capacitor materials. The first admixture is calcined to form an electrolyte precursor that is admixed with one or more additional components to form the solid-state electrolyte. When a ratio of the sulfate precursor to the one or more carbonaceous capacitor materials in the first admixture is about 1:2, the electrolyte precursor consists essentially of Li2S. When a ratio of the sulfate precursor to the one or more carbonaceous capacitor materials in the first admixture is less than about 1:2, the electrolyte precursor is a composite precursor including a solid-state capacitor cluster including the one or more carbonaceous capacitor materials and a sulfide coating including Li2S disposed on one or more exposed surfaces of the solid-state capacitor cluster.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for hierarchical weight-sparse convolution processing are described. An exemplary method comprises: obtaining an input tensor and a plurality of filters at a convolution layer of a neural network; segmenting the input tensor into a plurality of sub-tensors and assigning the plurality of sub-tensors to a plurality of processors; generating, for each of the plurality of filters, a hierarchical bit representation of a plurality of non-zero weights in the filter, wherein the hierarchical bit representation comprises a plurality of bits indicating whether a sub-filter has at least one non-zero weight, and a plurality of key-value pairs corresponding to the plurality of non-zero weights in the filter; identifying, based on the hierarchical bit representation, one or more of the plurality of non-zero weights and corresponding input values from the assigned sub-tensor to perform multiply-and-accumulate (MAC) operations.

Abstract: A material including TiO2 nanoparticles at least partially embedded in a matrix material of TixNbyOz, where 0<x?2, 0<y?24, and 0<z?62, is provided. Methods of making the material are also provided.

Abstract: A capacitor-assisted electrochemical cell according to various aspects of the present disclosure includes at least two first electrodes including one or more positive electroactive material layers disposed in electrical communication with a positive current collector; at least one second electrode including one or more first negative electroactive material layers disposed in electrical communication with a first negative current collector; and at least one composite electrode including one or more second negative electroactive material layers disposed in electrical communication with a second negative current collector. The second negative electroactive material layers may be in the form of a plurality of negative electroactive particles including one or more of a carbonaceous material and a metal oxide. Each negative electroactive particle may have a plurality of pores and a plurality of sulfur-additive particles disposed within the plurality of pores.