Abstract: In an embodiment, a softened solid-state electrolyte, comprises an oxide-based solid-state electrolyte, where at least a portion of the oxide anions in the oxide-based solid-state electrolyte is replaced with a replacement anion. In another embodiment, a softened solid-state electrolyte comprises a sulfide-based solid-state electrolyte, wherein at least a portion of the sulfide anions in the sulfide-based solid-state electrolyte is replaced with the replacement anion. When the replacement anion replaces the oxide anion, the replacement anion has a larger atomic radius than the oxide anion and when the replacement anion replaces the sulfide anion, the replacement anion has a larger atomic radius than the sulfide anion.

Abstract: The present disclosure relates to capacitor-assisted lithium-sulfur batteries including capacitor electrodes and/or capacitor-based interlayers. For example, a capacitor-assisted lithium-sulfur battery that includes two or more cells is provided. Each cell includes at least two electrodes selected from: a first electrode including a sulfur-containing electroactive material; a second electrode including a negative electroactive material; a first capacitor electrode including a positive capacitor active material; and a second capacitor electrode including a negative capacitor active material. Each electrode may be disposed adjacent to a surface of a current collector and a separator may be disposed between adjacent electrodes so as to provide electrical separation. One of the two or more cells includes the first electrode and the second electrode, and no cell includes both the first electrode and the first capacitor electrode or both the second electrode and the second capacitor electrode.

Abstract: The present disclosure relates to a solid-state electrochemical cell having a uniformly distributed solid-state electrolyte and methods of fabrication relating thereto. The method may include forming a plurality of apertures within the one or more solid-state electrodes; impregnating the one or more solid-state electrodes with a solid-state electrolyte precursor solution so as to fill the plurality of apertures and any other void or pores within the one or more electrodes with the solid-state electrolyte precursor solution; and heating the one or more electrodes so as to solidify the solid-state electrolyte precursor solution and to form the distributed solid-state electrolyte.

Abstract: A method for forming a bipolar solid-state battery includes preparing a mixture of gel precursor solution and solid electrolyte. The gel precursor includes a polymer, a first solvent, and a liquid electrolyte. The liquid electrolyte includes a second solvent, a lithium salt, and electrolyte additive. The method includes loading the mixture onto at least one of a first electrode, a second electrode, and a third electrode. Each of the first, second, and third electrodes includes a plurality of solid-state electroactive particles. The method includes removing at least a portion of the first solvent from the mixture to form a gel and positioning one of the first, second, and third electrodes with respect to another of the first, second, and third electrodes. The method includes applying a polymer blocker to a border of the first, second, or third electrodes.

Abstract: The present disclosure relates to an electrochemical cell having an elastic binding polymer that improves long-term performance of the electrochemical cell, particularly when the electrochemical cell includes an electroactive material that undergoes volumetric expansion and contraction during cycling of the electrochemical cell (such as, silicon-containing electroactive materials). The electrochemical cell can include the elastic binding polymer as an electrode additive and/or a coating layer disposed adjacent to an exposed surface of an electrode that includes an electroactive material that undergoes volumetric expansion and contraction and/or a gel layer disposed adjacent to an electrode that includes an electroactive material that undergoes volumetric expansion and contraction. The elastic binding polymer may include one or more alginates or alginate derivatives and at least one crosslinker.

Abstract: The present disclosure provides a solid-state bipolar battery that includes negative and positive electrodes having thicknesses between about 100 ?m and about 3000 ?m, and a solid-state electrolyte layer disposed between the negative electrode and the positive electrode and having a thickness between about 5 ?m and about 100 ?m. The first electrode includes a plurality of negative solid-state electroactive particles embedded on or disposed within a first porous material. The second electrode includes plurality of positive solid-state electroactive particles embedded on or disposed within a second porous material that is the same or different from the first porous material. The solid-state bipolar battery includes a first current collector foil disposed on the first porous material, and a second current collector foil disposed on the second porous material. The first and second current collector foils may each have a thickness less than or equal to about 10 ?m.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for convolution with workload-balanced activation sparsity are described. An exemplary method comprises: assigning an input tensor and a weight tensor at a convolution layer into a plurality of processors to perform Multiply-Accumulate (MAC) operations in parallel based on the input tensor and the weight tensor; obtaining a plurality of output values based on results of the MAC operations; constructing one or more banks of output values based on the plurality of output values; for each of the banks, performing a top-K sorting on the one or more output values in the bank to obtain K output values; pruning each of the banks by setting the one or more output values other than the obtained K output values in the each bank as zeros; and constructing an output tensor of the convolution layer based on the pruned banks.

Abstract: A solid-state electrochemical cell that cycles lithium ions is provide, where the electrochemical cell has an electrolyte layer in a solid-state or semi-solid state defining a first surface. A solid electrode having an electroactive material that defines a second surface is present. A hybrid capacitor material including a metal organic framework intermingled with solid-state electrolyte particles is disposed in at least one of the following: the solid electrode, an interfacial layer disposed between the first surface of the electrolyte and the second surface of the solid electrode, or both in the solid electrode and the interfacial layer.

Abstract: A high-temperature stable solid-state bipolar battery is provided. The battery includes two or more electrodes, one or more solid-state electrolyte layers, and an ionogel disposed within void spaces within the battery. Each electrode includes a plurality of solid-state electroactive particles. Each solid-state electrolyte layer includes a plurality of solid-state electrolyte particles and a first solid-state electrolyte layer of the one or more solid-state electrolyte layers may be disposed between a first electrode and a second electrode of the two or more electrodes. The ionogel is disposed within void spaces between the two or more electrodes, the solid-state electroactive particles of the two or more electrodes, the solid-state electrolyte particles of the one or more solid-state electrolyte layers, and the one or more solid-state electrolyte layers, such that the battery has an reduced interparticle porosity. The ionogel may have an ionic conductivity between about 0.1 mS/Cm and about 10 mS/cm.

Abstract: The disclosure relates to a buried bit line and a forming method thereof, the buried bit line is formed in a bit line slot of a substrate, the buried bit line includes a first bit line layer formed in the bit line slot, a first blocking layer and a second bit line layer. A top of the first bit line layer is lower than a surface of the substrate. The first blocking layer is at least partially formed between the first bit line layer and an inner wall of the bit line slot. The second bit line layer is formed in the bit line slot and configured to communicate the first bit line layer with a drain region in the substrate.

Abstract: A catalyst for oxidative coupling of methane, and preparation and application thereof. The catalyst comprises: a manganese sesquioxide, a tungstate, a manganese composite oxide having a perovskite structure and/or a spinel structure, and a carrier. The manganese sesquioxide, tungstate, and manganese composite oxide having a perovskite structure and/or a spinel structure are supported on the carrier, or the manganese sesquioxide and tungstate are supported on the admixture of the said manganese composite oxide having a perovskite structure and/or a spinel structure and the said carrier. Based on 100 parts by weight of the catalyst, the content of the manganese sesquioxide is a parts by weight, the content of the tungstate is b parts by weight, the content of the manganese composite oxide having the perovskite structure and/or the spinel structure is c parts by weight The content of the carrier is d parts by weight. 0<a?20, 1?b?20, 1?c?40, 20?d<98.

Abstract: A method for preparing a semiconductor structure includes: providing a semiconductor substrate; forming a groove in the semiconductor substrate; forming a first insulation layer, the first insulation layer at least covering an inner wall of the groove; forming a channel layer, the channel layer at least covering an inner wall of the first insulation layer; forming a second insulation layer, the second insulation layer at least covering an inner wall of the channel layer; filling the groove with a word line structure; removing part of the semiconductor substrate, part of the first insulation layer, and part of the channel layer, and forming a recess region in an outer side wall of the second insulation layer; and forming a source-drain in the recess region, the source-drain being electrically connected with the channel layer.

Abstract: A semiconductor device manufacturing method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region; depositing at least two insulating layers on a surface of the semiconductor substrate, each of the insulating layer has a different etch rate under a same etching condition; and removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of an upper insulating layer, and keeping all the insulating layers in the grooves located over the word line structures.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate, a trench and a word line. The substrate includes an isolation structure and an active area. The active area includes irons of a first type. The trench is arranged in the active area, an inner surface of the trench includes an inversion doping layer and an oxide layer which are arranged adjacent to each other, and the inversion doping layer is arranged above the oxide layer. The word line is arranged in the trench. The inversion doping layer includes ions of a second type. The first type is contrary to the second type.

Abstract: A capacitor structure and a method of manufacturing the same, and a memory are provided. The method includes the following operations. A substrate is provided. A first conductive structure with a shape of column is formed on the substrate. A second conductive structure is formed on the substrate. The second conductive structure surrounds the first conductive structure and is spaced with the first conductive structure. The first conductive structure and the second conductive structure together form a bottom electrode. A capacitor dielectric layer is formed. The capacitor dielectric layer covers the surface of the substrate and the surface of the bottom electrode. A top electrode covering the surface of the capacitor dielectric layer is formed.

Abstract: The present application relates to a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.

Abstract: A buried wordline structure fabrication method includes: providing a first trench in a semiconductor substrate, wherein the first trench has a tip on its bottom; performing epitaxial growth within the first trench to reduce the depth of the tip on the bottom of the first trench; and forming a gate dielectric layer on an inner wall of the first trench and filling a gate conductive layer within the first trench to form the buried wordline structure.

Abstract: A method for preparing a semiconductor device includes the following operations. A semiconductor substrate is provided, and a gate dielectric layer, a first conductive layer, and a support layer with a through hole are sequentially formed on the semiconductor substrate. A barrier layer and a second conductive layer are formed in the through hole. The support layer and a part of the first conductive layer located below the support layer are removed to form a primary gate pattern and expose the gate dielectric layer. A gate sidewall protective layer is formed on a sidewall of the primary gate pattern. An insulating layer is formed on a top of the primary gate pattern, a surface of the gate sidewall protective layer and a surface of the exposed part of the gate dielectric layer. A part of the insulating layer and a part of the gate dielectric layer are removed.

Abstract: A method for manufacturing a semiconductor structure includes the following operations. A first conductive layer, a second conductive layer and a passivation layer are successively formed on a semiconductor substrate. The passivation layer and the second conductive layer are patterned to form a primary gate pattern. A portion of the first conductive layer that is not covered by the primary gate pattern, is exposed. The primary gate pattern is subjected with plasma treatment to form a first protective layer. A dielectric layer is formed. The exposed portion of the first conductive layer is removed to retain a portion of the first conductive layer covered by the primary gate pattern. A second protective layer is formed on a side wall of the exposed portion of the first conductive layer.

Abstract: A method of making the sulfide-impregnated solid-state battery is provided. The method comprises providing a cell core that is constructed by cell unit. The cell core is partially sealed into the packaging such as the Al laminated film and metal can. The method further comprises introducing a sulfide solid-state electrolyte (S-SSE) precursor solution in the cell core, the S-SSE precursor solution comprises a sulfide solid electrolyte and a solvent. The method further comprises evaporating the solvent from the cell core to dry the cell core to solidify the sulfide-based solid-state electrolyte within the cell core and pressurizing the cell core to densify the solid sulfide-base electrolyte within the cell core. The cell core is then fully sealed.