Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for balanced-weight sparse convolution processing. An exemplary method comprises: obtaining an input tensor and a plurality of filters at a layer within a neural network; segmenting the input tensor into a plurality of sub-tensors; dividing a channel dimension of each of the plurality of filters into a plurality of channel groups; pruning each of the plurality of filters so that each of the plurality of channel groups of each filter comprises a same number of non-zero weights; segmenting each of the plurality of filters into a plurality of the sub-filters according to the plurality of channel groups; and assigning the plurality of sub-tensors and the plurality of sub-filters to a plurality of processors for parallel convolution processing.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a word line (WL) structure, wherein the substrate includes trenches arranged in parallel intervals; the WL structure is located in the trenches, and includes a dielectric layer and a conductive layer; the dielectric layer covers a bottom surface and a sidewall of the conductive layer; the conductive layer includes a first conductive layer and a second conductive layer; and a first component is doped in the second conductive layer.

Abstract: A battery system includes a battery cell, which includes an anode including a first current collector and an anode layer disposed on the first collector and including an anode active material. The cell includes a cathode including a second current collector and a cathode layer disposed on the second collector and including a cathode active material. The cell includes a solid-state electrolyte including one of a reduction tolerable solid electrolyte disposed in contact with the anode and an oxidation tolerable solid electrolyte disposed in contact with the cathode. The reduction tolerable solid electrolyte is present in an amount of from 0.1 part by weight to 5 parts by weight based upon 100 parts by weight of the anode layer. The oxidation tolerable solid electrolyte is present in an amount of from 1 part by weight to 10 parts by weight based upon 100 parts by weight of the cathode layer.

Abstract: A polymer gel electrolyte for an electrochemical cell that cycles lithium ions is provided. The polymer gel electrolyte includes a polymeric blend comprising polyvinylidene fluoride-hexafluoropropylene (PVDF-HFP) and polyvinylidene fluoride (PVDF), wherein a mass ratio of PVDF-HFP to PVDF is greater than or equal to about 1.5:1 to less than or equal to about 19:1 in the polymeric blend.

Abstract: A solid-state battery system including a graphite anode is provided. The system includes a battery cell. The battery cell includes the graphite anode, a cathode, and a solid electrolyte layer. The graphite anode includes a plurality of graphite particles, wherein the plurality of graphite particles includes a first portion of the plurality of graphite particles including a plurality of relatively high specific surface area graphite particles and a second portion of the plurality of graphite particles including a plurality of relatively low specific surface area graphite particles. The solid electrolyte layer is disposed between the graphite anode and the cathode and is operable to provide lithium-ion conduction path between the graphite anode and the cathode.

Abstract: The present disclosure provides a capacitor structure and a method for manufacturing same. The capacitor structure includes: a substrate, a first capacitor contact layer, a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer, where the first capacitor contact layer is arranged on the substrate in an array manner, the bottom electrode layer surrounds a side wall of the first capacitor contact layer and extends in a direction of the first capacitor contact layer away from the substrate, the capacitor dielectric layer covers an upper surface of the substrate, a surface of the bottom electrode layer and an upper surface of the first capacitor contact layer, and the top electrode layer covers a surface of the capacitor dielectric layer.

Abstract: A high-power gel-assisted battery stack that cycles lithium ions is provided with two terminal electrodes having opposite polarities and at least one bipolar electrode assembly disposed therebetween. A first electrode is disposed on a first side of a bipolar current collector and a second electrode with an opposite polarity to the first electrode is disposed on a second side of the bipolar current collector. Each electrode includes a porous layer having an electroactive material and a solid-state electrolyte disposed in a polymeric binder. A polymer gel electrolyte is distributed in pores of the porous. The stack also includes at least two free-standing gel separator layers each being disposed between the at least one bipolar electrode assembly and terminal electrodes. Each respective free-standing gel separator layer comprises polyacrylonitrile (PAN) and an electrolyte distributed therein. The high-power gel-assisted battery stack has a maximum voltage rating of ?about 12V.

Abstract: A positive electrode including an active layer is provided, where the active layer includes a plurality of positive electroactive solid-state particles, a lithium-source material coated on or dispersed with the positive electroactive solid-state particles in the active layer, and a polymeric gel electrolyte at least partially filling voids between the positive electroactive solid-state particles in the active layer. The lithium-source material having a theoretical specific capacity greater than or equal to about 100 mAh/g to less than or equal to about 3,000 mAh/g.

Abstract: Embodiments provide a semiconductor structure and a fabricating method. The semiconductor structure includes: a substrate, where a trench is formed in the substrate; a conductive layer positioned in the trench, where the conductive layer includes a first conductive layer and a second conductive layer, the second conductive layer is positioned on the first conductive layer, and a projection area of a bottom of the second conductive layer within the trench is greater than a projection area of a top of the first conductive layer within the trench; a dielectric layer positioned between the conductive layer and an inner wall of the trench, where a top of the dielectric layer is lower than the top of the first conductive layer; an isolation layer positioned on the conductive layer; and a void defined by the isolation layer, the conductive layer, the dielectric layer, and a side wall of the trench.

Abstract: The present disclosure provides a buried word line structure and a method for manufacturing the same, and a dynamic random access memory. The buried word line structure includes: a semiconductor substrate, word line trenches and word line structures. The semiconductor substrate is provided with active areas and shallow trench isolations, and the shallow trench isolations isolate the active areas. The word line trenches pass through the active areas along a first direction. The word line structures are disposed in the word line trenches. The word line structures include: a high dielectric constant dielectric layer covering inner surfaces of the word line trenches; a polysilicon layer covering the high dielectric constant dielectric layer; a work function layer covering the polysilicon layer; and a word line metal layer filled on a side of the work function layer away from the polysilicon layer.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for parallelizing convolution processing. An exemplary method comprises: segmenting an input tensor into a plurality of sub-tensors and a plurality of filters into a plurality of sub-filter groups; respectively assigning a plurality of combinations of the sub-tensors and the sub-filter groups to a plurality of processors; storing, by each of the plurality of processors, nonzero values of the sub-tensor and the sub-filter group in the assigned combination as index-value pairs; parallelly performing for a plurality of iterations, by the plurality of processors, multiply-and-accumulate (MAC) operations based on the index-value pairs to obtain a plurality of outputs, where the index-value pairs of the sub-filter groups are rotated among the plurality of processors across the plurality of iterations; and aggregating the plurality of outputs as an output tensor.

Abstract: The present disclosure provides a polymeric gel electrolyte for an electrochemical cell that cycles lithium ions. The polymeric gel electrolyte includes greater than or equal to about 0.1 wt. % to less than or equal to about 10 wt. % of a non-lithium salt. The non-lithium salt includes a non-lithium cation having an ion radius that is greater than or equal to about 80% to less than or equal to about 250% of an ion radius of a lithium ion. The polymeric gel electrolyte further includes greater than or equal to about 50 wt. % to less than or equal to about 99.9 wt. % of a non-volatile gel. The non-volatile gel includes greater than or equal to 0 wt. % to less than or equal to about 50 wt. % of a polymeric host and greater than or equal to about 5 wt. % to less than or equal to about 100 wt. % of a liquid electrolyte.

Abstract: The present disclosure relates to solid-state electrolytes and methods of making the same. The method includes admixing a sulfate precursor including one or more of Li2SO4 and Li2SO4.H2O with one or more carbonaceous capacitor materials. The first admixture is calcined to form an electrolyte precursor that is admixed with one or more additional components to form the solid-state electrolyte. When a ratio of the sulfate precursor to the one or more carbonaceous capacitor materials in the first admixture is about 1:2, the electrolyte precursor consists essentially of Li2S. When a ratio of the sulfate precursor to the one or more carbonaceous capacitor materials in the first admixture is less than about 1:2, the electrolyte precursor is a composite precursor including a solid-state capacitor cluster including the one or more carbonaceous capacitor materials and a sulfide coating including Li2S disposed on one or more exposed surfaces of the solid-state capacitor cluster.

Abstract: An anode-free solid-state battery includes a cathode layer having transient anode elements and a bare current collector devoid of non-transitory anode material and configured to accept thereon the transient anode elements. The battery also includes a solid-state electrolyte layer defining voids and arranged between the current collector and the cathode layer. The battery additionally includes a gel situated within the solid-state electrolyte and cathode layers, to permeate the electrolyte voids and form a gelled solid-state electrolyte layer, coat the cathode layer, and facilitate ionic conduction of the anode elements between the cathode layer, the solid-state electrolyte layer, and the current collector. Charging the battery diffuses the anode elements from the cathode layer, via the gelled solid-state electrolyte layer, onto the current collector. Discharging the battery returns the anode elements, via the gelled solid-state electrolyte layer, to the cathode layer.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The method for manufacturing a semiconductor device includes: providing a semiconductor substrate, with a plurality of trench isolation structures and a plurality of functional regions between the trench isolation structures being formed; forming a buried bit line structure, the buried bit line structure being formed in the semiconductor substrate; and forming a word line structure and a plurality of active regions, the word line structures and the active regions being formed on a surface of the semiconductor substrate and located above the functional regions.

Abstract: The present disclosure discloses a semiconductor device and a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes following steps: providing a semiconductor substrate, and forming active regions and trench isolation structures in the semiconductor substrate, wherein the trench isolation structures are located between the active regions; forming first grooves in the active regions; filling the first grooves to form inversion polysilicon layers, the inversion polysilicon layers being inversely doped with the active regions; forming second grooves, the second grooves running through the polysilicon layers and a part of the semiconductor substrate, and reserving parts of the inversion polysilicon layers located on side faces of the second grooves; and, forming buried word line structures in the second grooves.

Abstract: An electrochemical cell that cycles lithium ions is provided. The electrochemical cell includes a first electrode, a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. The first electrode includes a first plurality of solid-state electroactive material particles and a first polymeric gel electrolyte, where the first polymeric gel electrolyte includes a first additive. The second electrode includes a second plurality of solid-state electroactive material particles and a second polymeric gel electrolyte that is different from the first polymeric gel electrolyte, where the second polymeric gel electrolyte includes a second additive. The electrolyte layers include a third polymeric gel electrolyte that is different from both the first polymeric gel electrolyte and the second polymeric gel electrolyte.

Abstract: An anode electrode with enhanced state of charge estimation is provided. The anode electrode comprises anode layer and a negative current collector. The negative current collector has a first side and a second side. The anode layer comprises lithium-titanium oxide and a second anode material (e.g. niobium-titanium oxide) disposed on at least one of the first and second sides of the negative current collector with single-layer or layer-by-layer coated structures. The second anode material (e.g. niobium-titanium oxide) can be physically blended with lithium-titanium oxide or be at least partially coated on the surface of lithium-titanium oxide or their combinations. The anode electrode further comprises a binder and a conductive carbon.

Abstract: The present disclosure provides a method for making a solid-state argyrodite electrolyte represented by Li6PS5X (where X is selected from chloride, bromide, iodine, or a combination thereof) having an ionic conductivity greater than or equal to about 1.0×10?4 S/cm to less than or equal to about 10×10?3 S/cm at about 25° C. The method may include contacting a first suspension and a first solution to form a precursor, where the first suspension is a Li3PS4 suspension including an ester solvent and the first solution is a Li2S and LiX (where X is selected from chloride, bromide, or iodine, or a combination thereof) solution including an alcohol solvent; and removing the ester solvent and the alcohol solvent from the precursor to form the solid-state argyrodite electrolyte.

Abstract: Embodiments provide a semiconductor fabrication method. The method includes: providing a substrate including an active layer; and forming a bit line contact layer and a bit line extending along a first direction, two sides of the bit line contact layer being in contact with the active layer and the bit line. Forming the bit line includes: forming a bit line stack including a semiconductor layer and a conductive layer stacked in sequence, the semiconductor layer covering a surface of the substrate and a surface of the bit line contact layer; etching part of the bit line stack to form initial bit lines arranged at intervals, the initial bit lines including a plurality of conductive lines; performing oxidation treatment on the semiconductor layer exposed between adjacent conductive lines to form an oxide layer, the semiconductor layer not oxidized being used as a semiconductor connection layer; and removing the oxide layer.