Abstract: Provided are a device and a method for monitoring substrates to determine a processed state of the substrates and inspecting presence of abnormality in the processed substrates. A device for inspecting substrates includes a substrate mounting part moving relative to the substrate and for mounting a substrate, a measurement part for monitoring the substrate, a control part configured to control a movement path of the measurement part so that at least some regions are monitored from positions different from each other with respect to a plurality of substrates, and an analysis part configured to determine presence of abnormality from monitoring information about the plurality of substrates.

Abstract: A non-volatile memory device includes a substrate, a plurality of memory blocks grouped into pages, each including an alternating layer stack on the substrate, a plurality of channel holes in the alternating layer stack, and strings of memory cells disposed along the plurality of channel holes, and at least one dummy block adjacent to the plurality of memory blocks, each including an alternating dummy layer stack having multiple conductive layers and multiple dielectric layers alternately laminated on one another on the substrate, the at least one dummy block is disposed at an outskirt of each of the pages of the plurality of memory blocks.

Abstract: Provided are a device and a method for monitoring substrates to determine a processed state of the substrates and inspecting presence of abnormality in the processed substrates. A device for inspecting substrates includes a substrate mounting part moving relative to the substrate and for mounting a substrate, a measurement part for monitoring the substrate, a control part configured to control a movement path of the measurement part so that at least some regions are monitored from positions different from each other with respect to a plurality of substrates, and an analysis part configured to determine presence of abnormality from monitoring information about the plurality of substrates.

Abstract: A display apparatus including a panel substrate, a TFT panel part including a plurality of connection electrodes disposed on an upper surface of the panel substrate, and a light emitting diode part disposed on the TFT panel part and including a plurality of light emitting modules adjacent to each other, in which each of the light emitting modules includes a plurality of pixels, each of the pixels includes three sub-pixels, and the three sub-pixels include blue light emitting diodes, green light emitting diodes, and red light emitting diodes.

Abstract: A light emitting diode package is disclosed. The light emitting diode package includes a light emitting diode chip emitting light and a light transmissive member. The light transmissive member covers at least an upper surface of the light emitting diode chip and includes a light transmissive resin and reinforcing fillers. The reinforcing fillers have at least two side surfaces having different lengths and are dispersed in the light transmissive resin.

Abstract: A semiconductor device includes a first substrate, a second substrate, a first connection structure, and a second connection structure. A transistor is formed in a first side of the first substrate. A doped region is formed in a first side of the second substrate. The first connection structure is formed over a second side of the second substrate, and coupled to the doped region through a first VIA that extends from the second side of the second substrate to the doped region. The second connection structure is formed over the first side of the first substrate, connected with the first connection structure via a through silicon VIA, and coupled to the transistor through a bonding VIA. The first substrate is bonded to the second substrate by the bonding VIA, with the first side of the first substrate and the first side of the second substrate being facing each other.

Abstract: A display apparatus including a panel substrate, a TFT panel part including a plurality of connection electrodes disposed on an upper surface of the panel substrate, and a light emitting diode part disposed on the TFT panel part and including a plurality of light emitting modules adjacent to each other, in which each of the light emitting modules includes a plurality of pixels, each of the pixels includes three sub-pixels, and the three sub-pixels include blue light emitting diodes, green light emitting diodes, and red light emitting diodes.

Abstract: A method for interconnecting data between a plurality of blockchain networks according to an embodiment of the present invention includes receiving a request of an interconnecting transaction for interconnecting data between a plurality of blockchain networks, querying information of an ongoing or scheduled transaction through the plurality of blockchain networks in response to the request, and selectively determining any one of a plurality of interconnecting schemes as an interconnecting scheme of the interconnecting transaction with reference to the queried information, and performing the interconnecting transaction according to the determined interconnecting scheme.

Abstract: A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.

Abstract: A semiconductor device includes a first substrate having a first side for forming memory cells and an opposing second side, a doped region formed in the first side of the first substrate, a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, and a transistor formed in a first side of a second substrate and coupled to the first connection structure. The first VIA extends from the second side of the first substrate to the doped region. The memory cells include a plurality of word lines formed over the first side of the first substrate, a plurality of insulating layers disposed between the plurality of word lines, and a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers.

Abstract: A light emitting diode package is disclosed. The light emitting diode package includes a light emitting diode chip emitting light and a light transmissive member. The light transmissive member covers at least an upper surface of the light emitting diode chip and includes a light transmissive resin and reinforcing fillers. The reinforcing fillers have at least two side surfaces having different lengths and are dispersed in the light transmissive resin.

Abstract: A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.

Abstract: A light emitting diode package including: a housing; a light emitting diode chip arranged in the housing; a wavelength conversion unit arranged on the light emitting diode chip; a first fluorescent substance distributed inside the wavelength conversion unit and emitting light having a peak wavelength in the cyan wavelength band; and a second fluorescent substance distributed inside the wavelength conversion unit and emitting light having a peak wavelength in the red wavelength band, wherein the peak wavelength of light emitted from the light emitting diode chip is located within a range of 415 nm to 430 nm.

Abstract: A memory device includes a memory array, a circuit structure, a bonding structure between the memory array and the circuit structure, and a shielding structure between the memory array and the circuit structure and surrounding the bonding structure. The bonding structure includes a first bonding pattern and a second bonding pattern. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure includes a third bonding pattern and a fourth bonding pattern. The first bonding pattern is in contact with the second bonding pattern at a first interface between the first bonding pattern and the second bonding pattern. The third bonding pattern is in contact with the fourth bonding pattern at a second interface between the third bonding pattern and the fourth bonding pattern.

Abstract: A 3D-NAND memory includes a transistor formed in a first side of a periphery circuit substrate, a memory cell stack formed over a first side of a cell array substrate, and a first connection structure formed over an opposing second side of the cell array substrate. The memory cell stack includes a doped region formed in the first side of the cell array substrate and coupled to the first connection structure through a first VIA, a common source structure that extends from the doped region toward the first side of the periphery circuit substrate, and a second connection structure that is positioned over and coupled to the common source structure. The first side of the cell array substrate and the first side of the periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a first insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the first insulating structure. The 3D memory device further includes a first contact extending vertically from the second side of the substrate to be in contact with the first doped region.

Abstract: A light emitting diode package includes: a housing; a light emitting diode chip arranged in the housing; a wavelength conversion unit arranged on the light emitting diode chip; a first fluorescent substance distributed inside the wavelength conversion unit and emitting light having a peak wavelength in the cyan wavelength band; and a second fluorescent substance distributed inside the wavelength conversion unit and emitting light having a peak wavelength in the red wavelength band, wherein the peak wavelength of light emitted from the light emitting diode chip is located within a range of 415 nm to 430 nm.

Abstract: The display panel includes: a panel cover; an adhesive layer positioned below the panel cover; and a plurality of display modules detachably attached to the panel cover by the adhesive layer. The adhesive layer includes: a first adhesive layer positioned on the plurality of display modules, and a second adhesive layer positioned on the first adhesive layer. A peel strength of the second adhesive layer is greater than a peel strength of the first adhesive layer.

Abstract: An accelerated transaction processing apparatus includes a memory for storing one or more instructions, a communication interface for communicating with a blockchain network, and a processor. The processor is configured to determine whether the blockchain network is in a congested state based on monitoring information about the blockchain network, adjust a batch size based on a result of the determination, and perform batch processing for one or more individual transactions using the adjusted batch size.

Abstract: Memory device and formation method are provided. The memory device includes a substrate; a staircase structure on the substrate; a string driver structure over the staircase structure on a side opposite to the substrate; and a metal routing structure, between the string driver structure and the staircase structure along a vertical direction with respect to a lateral surface of the substrate. The staircase structure includes a plurality of word line tiers. The string driver structure includes a plurality of transistors to individually address the plurality of word line tiers. The string driver structure and the metal routing structure are vertically aligned with the staircase structure based on a lateral central region of the staircase structure.