Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region.

Abstract: A non-volatile memory device includes a substrate, a plurality of memory blocks grouped into pages, each including an alternating layer stack on the substrate, a plurality of channel holes in the alternating layer stack, and strings of memory cells disposed along the plurality of channel holes, and at least one dummy block adjacent to the plurality of memory blocks, each including an alternating dummy layer stack having multiple conductive layers and multiple dielectric layers alternately laminated on one another on the substrate, the at least one dummy block is disposed at an outskirt of each of the pages of the plurality of memory blocks.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region.

Abstract: A non-volatile memory device includes a plurality of memory blocks and a dummy block configured to form a pool capacitor for suppressing power noise. The dummy block includes a substrate, a conductor region in the substrate, and an alternating dummy layer stack on the conductor region. The alternating dummy layer stack includes multiple conductive layers and multiple dielectric layers alternately laminated on one another.

Abstract: The present disclosure relates to a stud improved to prevent loosening of the stud press-fitted into a sheet metal by increasing a resistance force against a torque. The stud includes a body provided to be inserted into a stud mounting hole formed on the sheet metal and formed with a screw thread to which a screw is fastened therein, a flange provided on one side of the body to have a larger diameter than the stud mounting hole and press-fitted into the sheet metal, and a rotation preventer protruding from the flange to have a diameter larger than the stud mounting hole and smaller than the flange and press-fitted into the sheet metal to prevent rotation of the stud, wherein the rotation preventer includes a plurality of rotation preventing protrusions having asymmetric shapes, and each of the plurality of rotation preventing protrusions includes a rotation preventing surface provided to be perpendicular to a tangent line of a circle connecting ends of the plurality of rotation preventing protrusions.

Abstract: One aspect of the present invention discloses a license authentication method in a wireless access point (AP). The method comprises receiving a license authentication request including license information from a client; calculating a distance of the client from the wireless access point in response to the received license authentication request; based on the calculated distance, determining whether the client exists within a range of allowed positions for license authentication related to license location information for allowing authentication of a license included in the license information; and determining whether to authenticate in response to the license authentication request based on the determination result.

Abstract: Disclosed is a display apparatus including a configuration for adjusting step difference of printed circuit boards (PCBs) on which a micro light emitting diode (Micro LED) is mounted.

Abstract: Memory device and formation method are provided. The memory device includes a substrate; a staircase structure on the substrate; a string driver structure over the staircase structure on a side opposite to the substrate; and a metal routing structure, between the string driver structure and the staircase structure along a vertical direction with respect to a lateral surface of the substrate. The staircase structure includes a plurality of word line tiers. The string driver structure includes a plurality of transistors to individually address the plurality of word line tiers. The string driver structure and the metal routing structure are vertically aligned with the staircase structure based on a lateral central region of the staircase structure.

Abstract: A method for interconnecting data between a plurality of blockchain networks according to an embodiment of the present invention includes receiving a request of an interconnecting transaction for interconnecting data between a plurality of blockchain networks, querying information of an ongoing or scheduled transaction through the plurality of blockchain networks in response to the request, and selectively determining any one of a plurality of interconnecting schemes as an interconnecting scheme of the interconnecting transaction with reference to the queried information, and performing the interconnecting transaction according to the determined interconnecting scheme.

Abstract: A semiconductor device includes a first substrate having a first side for forming memory cells and an opposing second side, a doped region formed in the first side of the first substrate, a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, and a transistor formed in a first side of a second substrate and coupled to the first connection structure. The first VIA extends from the second side of the first substrate to the doped region. The memory cells include a plurality of word lines formed over the first side of the first substrate, a plurality of insulating layers disposed between the plurality of word lines, and a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers.

Abstract: A 3D-NAND memory includes a transistor formed in a first side of a periphery circuit substrate, a memory cell stack formed over a first side of a cell array substrate, and a first connection structure formed over an opposing second side of the cell array substrate. The memory cell stack includes a doped region formed in the first side of the cell array substrate and coupled to the first connection structure through a first VIA, a common source structure that extends from the doped region toward the first side of the periphery circuit substrate, and a second connection structure that is positioned over and coupled to the common source structure. The first side of the cell array substrate and the first side of the periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.

Abstract: A memory device includes a memory array, a circuit structure, a bonding structure between the memory array and the circuit structure, and a shielding structure between the memory array and the circuit structure and surrounding the bonding structure. The bonding structure includes a first bonding pattern and a second bonding pattern. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure includes a third bonding pattern and a fourth bonding pattern. The first bonding pattern is in contact with the second bonding pattern at a first interface between the first bonding pattern and the second bonding pattern. The third bonding pattern is in contact with the fourth bonding pattern at a second interface between the third bonding pattern and the fourth bonding pattern.

Abstract: A semiconductor device is provided. The semiconductor device includes a first substrate that has a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device also includes a doped region and a first connection structure. The doped region is formed in the first side of the first substrate and is electrically coupled to at least a source terminal of a transistor (e.g., a source terminal of an end transistor of multiple transistors that are connected in series). The first connection structure is formed over the second side of the first substrate and coupled to the doped region through a first VIA. The first VIA extends from the second side of the first substrate to the doped region.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a first insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the first insulating structure. The 3D memory device further includes a first contact extending vertically from the second side of the substrate to be in contact with the first doped region.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region.

Abstract: A non-volatile memory device includes a first substrate, a second substrate, a memory array, a circuit structure, a bonding structure, and a shielding structure. A second front side of the second substrate faces a first front side of the first substrate. The memory array is disposed on the first substrate and disposed at the first front side of the first substrate. The circuit structure is disposed on the second substrate and disposed at the second front side of the second substrate. The bonding structure is disposed between the memory array and the circuit structure. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure is disposed between the memory array and the circuit structure and surrounds the bonding structure. The shielding structure is electrically connected to a voltage source.

Abstract: A non-volatile memory device includes a plurality of memory blocks and a dummy block configured to form a pool capacitor for suppressing power noise. The dummy block includes a substrate, a conductor region in the substrate, and an alternating dummy layer stack on the conductor region. The alternating dummy layer stack includes multiple conductive layers and multiple dielectric layers alternately laminated on one another.

Abstract: One aspect of the present disclosure provides a device for extracting and transmitting data from a shop floor image, the device comprising: an encoder configured for receiving, from a facility operating system, streaming video data of a display screen of a monitor of the facility operating system on a shop floor, and for encoding the streaming video data in real time; a video data analyzer configured for receiving the real-time encoded streaming video data and for extracting data by figuring out and tagging a data presentation location in the real-time encoded streaming video data using a video data analysis algorithm; and a communication unit configured for transmitting to a data engine the real-time encoded streaming video data, and the data extracted by the video data analyzer.

Abstract: A display apparatus including a panel substrate including a TFT drive circuit for active matrix driving, a plurality of light emitting diodes, and an anisotropic conductive film electrically connecting the light emitting diodes to the panel substrate, in which the anisotropic conductive film includes an adhesive organic insulation material and conductive particles dispersed in the adhesive organic insulation material.

Abstract: A light emitting diode apparatus including a substrate, a plurality of light emitting diodes regularly arranged on the substrate and configured to emit ultraviolet (UV) light, the light emitting diodes including first, second, and third sub-light emitting diodes, a plurality of phosphor layers disposed on the light emitting diodes and to convert the wavelength of light emitted from the light emitting diodes, the phosphor layers including first, second, and third phosphor layers disposed on the first, second, and third sub-light emitting diodes, respectively, and a control unit configured to supply power to the light emitting diodes, in which the phosphor layers are spaced apart from each other by a blocking region, and the control unit is configured to cause at least a portion of the light emitting diodes to emit light.