Abstract: A display device includes a display panel, a controller, and a data driver. The display panel includes a plurality of pixels. The controller is configured to: receive input image data for the display panel; divide the display panel into a plurality of first pixel blocks each having a first size; divide the display panel into a plurality of second pixel blocks each having a second size different from the first size; generate, based on the input image data, a first stress map for the plurality of first pixel blocks and a second stress map for the plurality of second pixel blocks; and generate output image data by compensating the input image data based on the first stress map and the second stress map. The data driver is configured to provide data voltages to the plurality of pixels based on the output image data.

Abstract: An electronic device comprises: a front housing including a display on a front surface; a rear housing located on a rear surface of the front housing; an antenna clip coupled to the rear housing, wherein the antenna clip may comprise: a coupling body coupled to one end of the rear housing; a first contact portion extending from the coupling body and electrically connected to an external radiator, and a second contact portion electrically connected to a circuit board between the front housing and the rear housing. Other various embodiments may be possible.

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

Abstract: An electronic device is disclosed herein.

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.

Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

Abstract: A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided, which may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An uplink transmission method is provided, which can increase an uplink coverage through improvement of reception reliability of uplink control information and data information.

Abstract: A ferroelectric memory device includes a channel layer, a gate insulation layer on the channel layer, and a gate electrode layer on the gate insulation layer. The gate insulation layer includes a ferroelectric inductive layer and a ferroelectric stack structure on the ferroelectric inductive layer, and the ferroelectric stack structure is stacked in an order or reverse order of a ferroelectric layer and a non-ferroelectric layer.

Abstract: A semiconductor memory device according to the present inventive concept includes: a semiconductor substrate; a common source semiconductor layer doped with impurities of a first conductivity type on the semiconductor substrate; a plurality of insulating layers and a plurality of word line structures alternately stacked on the common source semiconductor layer; and a memory cell dielectric layer penetrating the plurality of insulating layers and the plurality of word line structures and covering an internal wall of a channel hole extending in a vertical direction, and a memory cell structure filling the channel hole. The memory cell structure includes a channel layer, which has the memory cell dielectric layer thereon and fills at least a portion of the channel hole, and a drain layer covering an upper surface of the channel layer, doped with impurities of a second conductivity type, and filling some of an upper portion of the channel hole.

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a data storage layer including data storage devices, an interconnection layer disposed on the data storage layer, and a selection element layer provided between the data storage layer and the interconnection layer. The interconnection layer may include bit lines extending in a first direction. The selection element layer may include a cell transistor connected between one of the data storage devices and one of the bit lines, and the cell transistor may include an active pattern and a word line, which crosses the active pattern and is extended in a second direction crossing the first direction.

Abstract: The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.

Abstract: A semiconductor device may include first conductive lines on a substrate and spaced apart from each other in a first direction, second conductive lines spaced apart from the first conductive lines in a second direction, third conductive lines spaced apart from the second conductive lines in the second direction, gate electrodes between the first, second and third conductive lines and extending in the first direction, ferroelectric patterns on respective side surfaces of the gate electrodes, gate insulating patterns on the respective side surfaces of the gate electrodes and spaced apart from the respective side surfaces of the gate electrodes with the ferroelectric patterns respectively therebetween, and channel patterns extending along respective side surfaces of the gate insulating patterns. Each of the channel patterns may be electrically connected to the second conductive lines, respectively, and may be electrically connected to the first conductive lines or the third conductive lines, respectively.

Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.

Abstract: A 3D FeRAM device includes a capacitor structure including a first capacitor electrode on a substrate, the first capacitor electrode extending in a vertical direction substantially perpendicular to an upper surface of the substrate, a ferroelectric pattern surrounding a sidewall of the first capacitor electrode, and second capacitor electrodes surrounding and contacting an outer sidewall of the ferroelectric pattern, the second capacitor electrodes being spaced apart from each other in the vertical direction, an access transistor including a channel layer on the first capacitor electrode, a gate insulation layer surrounding an outer sidewall of the channel layer, and a gate electrode surrounding an outer sidewall of the gate insulation layer, a conductive pad on the channel layer, a contact plug on the conductive pad, and a bit line on the contact plug.

Abstract: A semiconductor device includes a source structure, a plurality of gate electrodes on the source structure.

Abstract: A display panel including a penetrating portion includes a substrate including a first region and a second region, which are spaced apart from each other with the penetrating portion provided therebetween, and a display element arranged on the substrate and including a first display element overlapping the first region and a second display element overlapping the second region, wherein a first side surface of the substrate that corresponds to an edge of the first region, and a second side surface of the substrate that corresponds to an edge of the second region, define at least portions of the penetrating portion, and an interval between the first side surface and the second side surface from an upper surface of the substrate, the upper surface facing the display element, is less than an interval between the first side surface and the second side surface from a lower surface of the substrate that does not face the display element.

Abstract: A display apparatus includes: a substrate including a first surface, a second surface opposite the first surface, a display area defined on the first surface, and a non-display area defined on the second surface; a plurality of display elements at the display area on the first surface of the substrate; a driving circuit on the second surface and overlapping with the display area of the substrate; a first conductive pattern on the second surface of the substrate; and a second conductive pattern on the first surface of the substrate and connected to the first conductive pattern via a contact hole extending through the substrate. A surface roughness of the second surface of the substrate is greater than a surface roughness of the first surface of the substrate.