Abstract: A semiconductor memory device may include a substrate, first and second impurity regions on the substrate, first and second gate insulating layers sequentially stacked on the substrate and extended in a direction between the first and second impurity regions, and a gate electrode on the second gate insulating layer. The first and second impurity regions may have different conductivity types from each other, a bottom surface of the first gate insulating layer may be in direct contact with a top surface of the substrate, and the second gate insulating layer may include a ferroelectric material.

Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.

Abstract: Disclosed is a semiconductor memory device including a substrate, a plurality of source lines extending in a first direction on the substrate, a plurality of word lines crossing the source lines and extending in a second direction different from the first direction, a plurality of bit lines crossing the source lines and the word lines and extending in a third direction different from the first direction and the second direction, and a plurality of memory cells disposed at intersections between the source lines, the word lines, and the bit lines. The first, second, and third directions are parallel to a top surface of the substrate.

Abstract: A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.

Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

Abstract: A semiconductor device includes a plurality of gate electrodes extending on a substrate in a first horizontal direction and each including first and second vertical extension sidewalls that are opposite to each other, a channel arranged on the first vertical extension sidewall of each gate electrode and including a vertical extension portion, a ferroelectric layer and a gate insulating layer that are sequentially located between the channel layer and the first vertical extension sidewall of each gate electrode, an insulating layer on the second vertical extension sidewall of each gate electrode, and a plurality of bit lines electrically connected to the channel layer and extending in a second horizontal direction that is different from the first horizontal direction.

Abstract: A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.

Abstract: A negative active material for a rechargeable lithium battery and a rechargeable lithium battery, the negative active material includes a porous silicon-carbon composite that includes silicon, carbon, and magnesium silicate (MgSiO3), wherein the negative active material has a diffraction peak intensity ratio IMgSiO3(610)/ISi(111) of 0.001<IMgSiO3(610)/ISi(111)<0.01, which is a ratio of a diffraction peak intensity IMgSiO3(610) by MgSiO3 at 2?=30° to 32° to a diffraction peak intensity ISi(111) by Si(111) detected at 2?=27.5° to 29.5° in a X-ray diffraction analysis.

Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided, which may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An uplink transmission method is provided, which can increase an uplink coverage through improvement of reception reliability of uplink control information and data information.

Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.

Abstract: A semiconductor device including a substrate including a cell array region and a connection region, an electrode structure stacked on the substrate, each of the electrodes including a line portion on the cell array region and a pad portion on the connection region, Vertical patterns penetrating the electrode structure, a cell contact on the connection region and connected to the pad portion, an insulating pillar below the cell contact, with the pad portion interposed therebetween may be provided. The pad portion may include a first portion having a top surface higher than the line portion, and a second portion including a first protruding portion, the first protruding portion extending from the first portion toward the substrate and covering a top surface of the insulating pillar.

Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer.

Abstract: A display device includes a substrate having a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface; a thin film transistor disposed above the top surface and including a semiconductor layer; a display element connected to the thin film transistor; a top conductive pattern disposed between the substrate and the thin film transistor and overlapping the semiconductor layer of the thin film transistor; a bottom conductive pattern disposed on the bottom surface and connected to the top conductive pattern through the first contact hole; and a bottom planarization layer disposed on the bottom surface, the bottom planarization layer disposed on the bottom conductive pattern.

Abstract: The present disclosure relates to a communication technique for convergence of a 5G communication system for supporting a higher data transmission rate beyond a 4G system with an IoT technology, and a system therefor. The present disclosure may be applied to an intelligent service (for example, smart home, smart building, smart city, smart car or connected car, health care, digital education, retail business, security and safety-related service, etc.) on the basis of a 5G communication technology and an IoT related technology. The present invention relates to a method for controlling power of a terminal in a beamforming system and, specifically, provides a method for supporting control of uplink power of a terminal according to a beam change.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a substrate; a transistor disposed above the substrate, the transistor having a channel region defining an inner space; and a capacitor passing through the transistor in a vertical direction in the inner space.

Abstract: A memory device includes a magnetic track layer extending on a substrate, the magnetic track layer having a folded structure that is two-dimensionally villi-shaped, a plurality of reading units including a plurality of fixed layers and a tunnel barrier layer between the magnetic track layer and each of the plurality of fixed layers, and a plurality of bit lines extending on different ones of the plurality of reading units, the plurality of reading units being between the magnetic track layer and corresponding ones of the plurality of bit lines.

Abstract: A semiconductor device includes first conductive lines provided on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, second conductive lines spaced apart from the first conductive lines in a second direction parallel to the top surface of the substrate, a gate electrode disposed between the first and second conductive lines and extended in the first direction, a plurality of channel patterns provided to enclose a side surface of the gate electrode and spaced apart from each other in the first direction, a ferroelectric pattern between each of the channel patterns and the gate electrode, and a gate insulating pattern between each of the channel patterns and the ferroelectric pattern. Each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.

Abstract: A semiconductor device includes a plurality of first conductive lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, the first direction and second direction being horizontal directions, a plurality of vertical semiconductor patterns disposed on the plurality of first conductive lines, respectively, a gate electrode crossing the plurality of first conductive lines and penetrating each of the plurality of vertical semiconductor patterns, a ferroelectric pattern between the gate electrode and each of the plurality of vertical semiconductor patterns, and a gate insulating pattern between the ferroelectric pattern and each of the plurality of vertical semiconductor patterns.

Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.