Abstract: A thin film transistor array panel may include a channel layer including an oxide semiconductor and formed in a semiconductor layer, a source electrode formed in the semiconductor layer and connected to the channel layer at a first side, a drain electrode formed in the semiconductor layer and connected to the channel layer at an opposing second side, a pixel electrode formed in the semiconductor layer in a same portion of the semiconductor layer as the drain electrode, an insulating layer disposed on the channel layer, a gate line including a gate electrode disposed on the insulating layer, a passivation layer disposed on the source and drain electrodes, the pixel electrode, and the gate line, and a data line disposed on the passivation layer. A width of the channel layer may be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.

Abstract: A thin film transistor includes a bottom gate electrode, a top gate electrode and an active pattern. The top gate electrode includes a transparent conductive material and overlaps with the bottom gate electrode. A boundary of the bottom gate electrode and a boundary of the top gate electrode are coincident with each other in a cross-sectional view. The active pattern includes a source portion, a drain portion and a channel portion disposed between the source portion and the drain portion. The channel portion overlaps with the bottom gate electrode and the top gate electrode.

Abstract: A thin film transistor array panel includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern disposed on the base substrate, a gate insulation pattern disposed on the active pattern, a gate electrode disposed on the gate insulation pattern and overlapping the channel, and a light-blocking pattern disposed between the base substrate and the active pattern and having a size greater than the active pattern. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode.

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract: A light-emitting device comprises a textured substrate comprising a plurality of textured structures, wherein the textured structures and the textured substrate are both composed of sapphire; and a light-emitting stack overlaying the textured substrate, comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, wherein each of the plurality of textured structures comprises a top portion having a first top-view shape, and a bottom portion parallel to the top portion and having a second top-view shape, wherein the first top-view shape comprises a circle or an ellipse, the first top-view shape comprises a first periphery and the second top-view shape comprises a second periphery, the first periphery is enclosed by the second periphery, and various distances are between each of the first periphery and the second periphery.

Abstract: A display apparatus including a display panel connected to a plurality of data lines, a data driver configured to generate a plurality of data voltages, and to apply the plurality of data voltages to the plurality of data lines, and a plurality of feedback lines disposed in a fan-out region between the display panel and the data driver, wherein the data driver is further configured to applies a first signal to each of the plurality of feedback lines, wherein delays by the fan-out region are obtained based on the first signal, the delays being associated with the plurality of data lines, and wherein the data driver is further configured to controls output times of the plurality of data voltages based on the delays.

Abstract: A method of forming a conductive pattern includes forming a trench on a substrate, and providing a conductive ink to the trench while an electric field is generated between the substrate and a nozzle which ejects the conductive ink.

Abstract: Disclosed is an additive for a non-aqueous electrolyte, which is a compound having a double bond and at least two cyano groups, the two cyano groups being in a trans-formation to the double bond. Also, a non-aqueous electrolyte comprising the additive and an electrochemical device comprising the non-aqueous electrolyte are also disclosed. Further, an electrode comprising the cyano group-containing compound and an electrochemical device comprising the electrode are disclosed.

Abstract: A thin film transistor display panel includes: a gate electrode, a source electrode and a drain electrode which are included in a thin film transistor on a substrate; a data line connected to the source electrode; a pixel link member connecting the drain electrode to a pixel electrode; and a gate pad connected to the gate electrode through a gate line and including a first gate subpad, a second gate subpad and a gate pad link member, in which the pixel link member and the gate pad link member are substantially same in thickness.

Abstract: A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.

Abstract: Provided is lithium disilicate crystalline glass containing cristobalite crystal phase for high strength and aesthetic traits and its manufacturing process thereof. Exemplary embodiments of the present invention provide the high strength and aesthetic lithium disilicate crystalline glass, one kind of dental restoration materials, and its manufacturing method which induces the growth of the different crystal phase, cristobalite, from glass with lithium disilicate crystal.

Abstract: A thin film transistor substrate includes a base substrate, an active pattern disposed on the base substrate, a gate insulation pattern disposed on the active pattern, a gate electrode disposed on the gate insulation pattern and overlapping the channel, and a light-blocking pattern disposed between the base substrate and the active pattern and having a size greater than the active pattern. The active pattern includes a source electrode, a drain electrode, and a channel disposed between the source electrode and the drain electrode.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: The present invention relates to an iodine (I2) or bromine (Br2) adsorbent including a zeolite having a Si/Al ratio of 15 or greater; an I2 or Br2 carrier including the I2 or Br2 adsorbent; a column filled with the I2 or Br2 adsorbent; a article composed of the I2 or Br2 adsorbent or having the I2 or Br2 adsorbent attached thereto; a method for adsorbing or removing I2 or Br2 using the I2 or Br2 adsorbent; an iodine- or bromine-containing zeolite composite including a porous zeolite and iodine (I2) or bromine (Br2) confined in the pores of the zeolite; a semiconductor material including the iodine- or bromine-containing zeolite composite; and a method for preparing an iodine- or bromine-containing product using the iodine- or bromine-containing zeolite composite.

Abstract: A single external power supply variable speed induction motor and a control method thereof are disclosed. An induction motor includes: a stator in which coils directly connected to a single-phase or 3-phase or more systematic power supply are wound; a rotor that is supported to be rotatable in the stator; a power conversion device that is attached to the rotor and controls a rotor current without connection of a separate external power supply; and a control circuit that is connected to the power conversion device and controls the power conversion device.

Abstract: Provided is a thin film transistor array panel. The thin film transistor array panel according to exemplary embodiments of the present invention includes: a gate wiring layer disposed on a substrate; an oxide semiconductor layer disposed on the gate wiring layer; and a data wiring layer disposed on the oxide semiconductor layer, in which the data wiring layer includes a main wiring layer including copper and a capping layer disposed on the main wiring layer and including a copper alloy.

Abstract: A light-emitting device comprises a textured substrate comprising a boundary and a plurality of textured structures within the boundary, wherein the textured structures and the textured substrate are both composed of sapphire; and a light-emitting stack overlaying the textured substrate, comprising a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer, wherein each of the plurality of textured structures comprises a top portion having a first top-view shape and a bottom portion parallel to the top portion, the bottom portion having a second top-view shape, wherein the first top-view shape comprises a circle or ellipse and the second top-view shape comprises a polygon, wherein the first top-view shape and the second top-view shape overlap each other, and the textured structures are spaced apart from each other from a top view of the light-emitting device.

Abstract: The inventive concepts provide a substrate treating apparatus. The apparatus includes a process chamber, a substrate support unit, a gas supply unit, a microwave applying unit, an antenna plate, a slow-wave plate, a dielectric plate, and an exhaust baffle, and a liner. The liner includes a body having a ring shape facing an inner sidewall of the process chamber, and a flange extending from the body into a wall portion of the process chamber. The flange prevents an electric field of a microwave and a process gas from being provided into a gap between the process chamber and the body. Thus, it is possible to inhibit particles from being generated by damage of the inner sidewall of the process chamber by plasma, and drift distances of the particles can be reduced to inhibit the particles from reaching a substrate.

Abstract: A touch sensing type liquid crystal display device includes an array substrate includes an array substrate including a first substrate, a common electrode, a pixel electrode, and a touch sensing unit; a color filter substrate including a second substrate and facing the array substrate; an anti-static layer on an outer side of the second substrate and including an inorganic material and conductive particles; and a liquid crystal layer between the first substrate and an inner side of the second substrate.