Abstract: A display panel includes: first and second display areas; first and second pixel circuits connected to light-emitting elements in the first and second display areas, respectively; and first pixel units and second pixel units, each first pixel unit comprising a first pixel circuit and a light-emitting element connected to the first pixel circuit, and each second pixel unit comprising a second pixel circuit and a light-emitting element connected to the second pixel circuit, wherein each first pixel unit includes the light-emitting element emitting light of a first color, each second pixel unit includes the light-emitting element emitting light of a second color, the first color is different from the second color, each first pixel unit is configured to receive a first power supply signal and a second power supply signal, and each second pixel unit is configured to receive a third power supply signal and a fourth power supply signal.

Abstract: A data transmission method is provided, where the method includes: receiving a user datagram protocol (UDP) data packet transmitted by a client; determining a target second thread from n second threads through a first thread, where the n second threads are configured for processing the UDP data packet, and the target second thread is configured for managing a QUIC connection corresponding to the UDP data packet; and transferring the UDP data packet to the target second thread through the first thread. The second threads are scheduled by the first thread, and different second threads may manage different QUIC connections, so that QUIC connections are managed through different threads. Therefore, a server can fully utilize a concurrent processing capability of a plurality of cores, which improves the efficiency of managing QUIC connections and the data transmission performance.

Abstract: A display panel includes a driver circuit including shift registers with N stages and being cascade with each other, where N?2, and each shift register includes a first control portion and a second control portion. The first control portion is configured to control a first output signal, where the first output signal of an i-th stage of shift register is an input signal of a j-th stage of shift register, and 1?i?N, 1?j?N. The second control portion is configured to receive at least the first output signal and a frequency control signal and control a second output signal. In a case where the first output signal is an effective pulse and a time period of the effective pulse is within a time period of an effective pulse of the frequency control signal, the second output signal is the effective pulse.

Abstract: A data caching method comprises: receiving message data returned by a second device in response to a read command; dividing the message data into two paths of data according to a preset strategy, sending one of the two paths of data to a first random access memory for storage, and distributing the other path to a double data rate synchronous dynamic random access memory for storage through a first input first output queue, wherein a sum of a working bandwidth of the first random access memory and a working bandwidth of the double data rate synchronous dynamic random access memory is greater than or equal to a receiving bandwidth of the message data; and sending data stored in the first random access memory and data stored in the double data rate synchronous dynamic random access memory to a first device connected with network equipment.

Abstract: Provided are a display panel. When a bias adjustment control signal is an effective pulse signal, a bias adjustment module is on and provides a bias adjustment signal for a drive transistor. The data refresh rate of a first pixel circuit is a first frequency F1. The data refresh rate of a second pixel circuit is a second frequency F2. F1?F2. A data refresh period of the first pixel circuit includes R1 image refresh frames. A data refresh period of the second pixel circuit includes R2 image refresh frames. The sum of time durations of effective pulses of the bias adjustment control signal is Ws1 in the data refresh period of the first pixel circuit. The sum of time durations of effective pulses of the bias adjustment control signal is Ws2 in the data refresh period of the second pixel circuit. Ws1/R1?Ws2/R2.

Abstract: A display substrate, a display panel and a display device are provided. The display substrate is divided into a display region and a non-display region at least partially surrounding the display region. The display substrate includes data cables and adapter cables arranged in the display region, and connecting cables arranged in the non-display region. A part of the connecting cables are electrically connected to a part of the data cables through the adapter cables, and the remaining connecting cables are electrically connected to the remaining data cables directly. The data cables and the connecting cables are both arranged in the first direction. The data cables are arranged in a same sequence as the connecting cables electrically connected to the data cables. Therefore, performance of the display can be optimized.

Abstract: A display panel includes a pixel circuit and a driving circuit. The pixel circuit includes a driving transistor. The driving circuit is configured to provide a signal for the pixel circuit, receive a third voltage signal and a fourth voltage signal, and generate an output signal. The third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal. A working process of the pixel circuit includes a reset phase and a bias phase. The output signal of the driving circuit is a reset signal in the reset phase. The output signal of the driving circuit is a bias signal in the bias phase. In response to the driving transistor being a PMOS transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. A shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit comprises a first gating unit. One terminal of the first gating unit is connected to a preset node, another terminal of the first gating unit is connected to a fourth node, and a control terminal of the first gating unit is configured to receive a fifth voltage signal. The second control unit is configured to receive at least a third voltage signal and a signal of the fourth node or receive at least a fourth voltage signal and a signal of a fifth node and generate an output signal.

Abstract: Provided are an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes: a substrate, a first active layer of a first thin film transistor, a first insulating layer, a first metal layer, and a second active layer of a second thin film transistor. The first metal layer includes a first connection portion, which overlaps one of a source contact region or a drain contact region of the first active layer and overlaps one of a source contact region or a drain contact region of the second active layer. The one of the source contact region or the drain contact region of the first active layer and the one of the source contact region or the drain contact region of the second active layer overlap each other, and are electrically connected through a via in the first insulating layer and the first connection portion.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. A shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit is configured to receive at least a signal of a preset node and a first output control signal and control a signal of a fourth node. During at least part of a time period during which the signal of the fourth node is a low level signal, each of a signal of the preset node and the first output control signal is a low level signal.

Abstract: The present disclosure discloses a detection kit for Salmonella typhi, a preparation method and an application thereof, the detection kit includes: amplification primer, crRNA, LbCas12a-RR protein and a single-stranded DNA reporting system, the crRNA is a specific crRNA for a detection segment of the flag gene of Salmonella typhi; a LbCas12a-RR protein expression sequence is a prokaryotic codon optimized with a Cas12 protein nucleic acid sequence, and amino acid positions of 532 and 595 are mutated into G532R and K595R, respectively. The application of the kit is, to use the detection kit of Salmonella typhi for nucleic acid detection of Salmonella typhi; and the kit has high sensitivity, high specificity and fast visualization.

Abstract: A display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, N?2. A shift register of the N levels of the shift registers includes a third control unit and a fourth control unit. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node. The first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The fourth control unit is configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the first node and the signal of the fourth node and includes a first transistor and a second transistor.

Abstract: The application provides a display panel, integrated chip component and display device. The display panel includes: a first display area and a second display area; pixel circuits comprising first pixel circuits and second pixel circuits, the first pixel circuits and the second pixel circuits being configured to provide driving currents for light-emitting elements in the first display area and the second display area, respectively; and first pixel units and second pixel units, each first pixel unit comprising a first pixel circuit and a light-emitting element connected to the first pixel circuit, and each second pixel unit comprising a second pixel circuit and a light-emitting element connected to the second pixel circuit; wherein each first pixel unit is configured to receive a first power supply signal V1 and a second power supply signal V2, V1>V2.

Abstract: A display panel and a display device are provided. The display panel includes a substrate, signal lines located on the substrate, and a plurality of light-emitting elements each located on a side of one of the signal lines facing away from the substrate. Each light-emitting element includes a first electrode, a light-emitting layer, and a second electrode that are stacked sequentially. Each signal line includes at least one overlapping portion overlapping the light-emitting layer of one of the light-emitting elements in a direction perpendicular to the display panel. An angle ? between an extending direction of a part of the at least one overlapping portion and a pixel column direction in a display region that satisfies: 0°<?<90°, or an angle ? between an extending direction of a tangent of a part of the at least one overlapping portion and a pixel column direction in a display area that satisfies: 0°<?<90°.

Abstract: Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region. The pixel circuit includes a drive transistor and a first presetting module, and a terminal of the first presetting module is connected to the drive transistor, where a control terminal of a first presetting module in the first pixel circuit is configured to receive a first control signal, and a control terminal of a first presetting module in the second pixel circuit is configured to receive a second control signal.

Abstract: Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region.

Abstract: Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region. The pixel circuit includes a drive transistor and a first presetting module, and a terminal of the first presetting module is connected to the drive transistor, where a control terminal of a first presetting module in the first pixel circuit is configured to receive a first control signal, and a control terminal of a first presetting module in the second pixel circuit is configured to receive a second control signal.

Abstract: A display panel includes a shift register, a pixel circuit, and a driving circuit. The shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node.

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit including a driving transistor and a preset module, a light-emitting element, and a gating module. A first terminal of the preset module is connected to the driving transistor, a second terminal of the preset module is connected to a preset signal terminal or the driving transistor, a control terminal of the preset module is connected to a control signal line, and the control signal line is configured to receive a control signal. The gating module is connected to a gating signal line, and the gating signal line is configured to receive a gating signal. In at least a portion of an operation process of the display panel, a pulse change frequency of the gating signal is F, and a pulse change frequency of the control signal is Fc, and F?Fc.

Abstract: Provided are an array substrate and a manufacturing method of an array substrate and a display panel and device. The array substrate includes a pixel circuit. The pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon. The array substrate further includes a first-type inorganic layer and a second-type inorganic layer and a first via hole. The first via hole is located above the first active layer and at least penetrates through the second-type inorganic layer. Concentration of hydrogen ions in the first active layer is less than concentration of hydrogen ions in the second active layer.