Abstract: Provided are an array substrate and a manufacturing method of an array substrate and a display panel and device. The array substrate includes a pixel circuit. The pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon. The array substrate further includes a first-type inorganic layer and a second-type inorganic layer and a first via hole. The first via hole is located above the first active layer and at least penetrates through the second-type inorganic layer. Concentration of hydrogen ions in the first active layer is less than concentration of hydrogen ions in the second active layer.

Abstract: A display panel and a display device are provided. The display panel includes a substrate, signal lines located on the substrate, and a plurality of light-emitting elements each located on a side of one of the signal lines facing away from the substrate. Each light-emitting element includes a first electrode, a light-emitting layer, and a second electrode that are stacked sequentially. Each signal line includes at least one overlapping portion overlapping the light-emitting layer of one of the light-emitting elements in a direction perpendicular to the display panel. An angle ? between an extending direction of a part of the at least one overlapping portion and a pixel column direction in a display region that satisfies: 0°<?<90°, or an angle ? between an extending direction of a tangent of a part of the at least one overlapping portion and a pixel column direction in a display area that satisfies: 0°<?<90°.

Abstract: A display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a driving module, a data-writing module, and a compensation module, and a reset module. The driving module includes a driving transistor. The data-writing module is connected to a source of the driving transistor and configured to selectively provide a data signal for the driving transistor. The compensation module is connected between a gate and a drain of the driving transistor. The reset module is connected between the drain of the driving transistor and a reset signal terminal and configured to provide a reset signal for the gate of the driving transistor. The reset module is used as a bias module. An operating process of the pixel circuit includes a reset stage and a bias stage.

Abstract: Disclosed is a banknote accumulating device, including a storage chamber and a limiting mechanism arranged above the storage chamber; the storage chamber includes an inlet for inputting banknotes; the limiting mechanism includes a reset member, a driving mechanism and multiple limiting members which can move independently of each other; the reset member is configured to enable each of limiting members to have a tendency to move to a first position; the driving mechanism is configured to selectively drive one of the multiple limiting members to move from a first position to a second position, so that the limiting part of the limiting member reaches in the moving path of the banknotes in the storage chamber; the distances between the positions of the limiting parts of multiple limiting members in the moving path and the inlet are different. Further disclosed are a limiting mechanism and a cash recycling and handling device.

Abstract: Disclosed are a gate mechanism and a cash recycling and handling device. The gate mechanism includes a frame with an opening, a driving door and a driven door both of which are movably connected to the frame, where the driving door can be located at a first position and a second position, and the driven door can be located at a third position and a fourth position; when the driving door is located at the first position and the driven door is located at the third position, the driving door and the driven door jointly close the opening; when the driving door is located at the second position and the driven door is located at the fourth position, the driving door and the driven door jointly open the opening, and the driven door at the fourth position, the driving door at the second position and a panel are sequentially stacked.

Abstract: Provided are an array substrate and a manufacturing method of an array substrate and a display panel and device. The array substrate includes a pixel circuit. The pixel circuit includes a first transistor and a second transistor, the first transistor includes a first active layer, the second transistor includes a second active layer, and the first active layer and the second active layer both include silicon. The array substrate further includes a first-type inorganic layer and a second-type inorganic layer and a first via hole. The first via hole is located above the first active layer and at least penetrates through the second-type inorganic layer. Concentration of hydrogen ions in the first active layer is less than concentration of hydrogen ions in the second active layer.

Abstract: Provided are a display panel, an integrated chip, and a display device. The display panel includes a first display region, a second display region, and a pixel circuit. The pixel circuit includes a first pixel circuit and a second pixel circuit, where the first pixel circuit is connected to a light-emitting element in the first display region, and the second pixel circuit is connected to a light-emitting element in the second display region. The pixel circuit includes a drive transistor and a first presetting module, and a terminal of the first presetting module is connected to the drive transistor, where a control terminal of a first presetting module in the first pixel circuit is configured to receive a first control signal, and a control terminal of a first presetting module in the second pixel circuit is configured to receive a second control signal.

Abstract: Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded, wherein N is a number greater than or equal to 2; where the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control unit comprising a first capacitor, a first transistor and a second transistor, where a second plate of the first capacitor is connected to a drain of the first transistor, a source of the second transistor is connected to a first node, and a drain of the second transistor is connected to the third node.

Abstract: Provided is a display panel, and the display panel includes a base substrate, a first signal line, a planarization layer, a light-emitting element and a pixel spacer layer. The first signal line is disposed on the base substrate, where the first signal line includes a first sub signal line and a second sub signal line which are electrically connected to each other and are disposed in different layers, and the first sub signal line is disposed on one side of the second sub signal line facing toward the base substrate. The planarization layer is disposed on one side of the first signal line facing away from the base substrate. The light-emitting element and the pixel spacer layer are disposed on one side of the planarization layer facing away from the base substrate. The planarization layer includes a first opening.

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit including a driving transistor and a preset module, a light-emitting element and a gating module. A first terminal of the preset module is connected to the driving transistor, and a second terminal of the preset module is connected to a preset signal terminal or the driving transistor, a control terminal of the preset module is connected to a control signal line, a control terminal of the gating module is connected to a gating signal line configured for receiving a gating signal, the gating module is connected between the control terminal of the preset module and the control signal line, or between the first terminal of the preset module and the driving transistor, or between the second terminal of the preset module and the preset signal terminal or the driving transistor.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module and a compensation module. The drive module includes a drive transistor. The data write module is connected to an input terminal of the drive module; a first electrode of the compensation module is connected to an output terminal of the drive module, and a second electrode of the compensation module is connected to a control terminal of the drive module. The data write module includes a data write transistor and a bias transistor, the data write transistor is connected to a data signal input terminal and configured to transmit a data signal, and the bias transistor is connected to a bias signal input terminal and configured to transmit a bias signal.

Abstract: The present disclosure discloses a detection kit for Salmonella typhi, a preparation method and an application thereof, the detection kit includes: amplification primer, crRNA, LbCas12a-RR protein and a single-stranded DNA reporting system, the crRNA is a specific crRNA for a detection segment of the flag gene of Salmonella typhi; a LbCas12a-RR protein expression sequence is a prokaryotic codon optimized with a Cas12 protein nucleic acid sequence, and amino acid positions of 532 and 595 are mutated into G532R and K595R, respectively. The application of the kit is, to use the detection kit of Salmonella typhi for nucleic acid detection of Salmonella typhi; and the kit has high sensitivity, high specificity and fast visualization.

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit including a driving transistor and a preset module, a light-emitting element and a gating module. A first terminal of the preset module is connected to the driving transistor, and a second terminal of the preset module is connected to a preset signal terminal or the driving transistor, a control terminal of the preset module is connected to a control signal line, a control terminal of the gating module is connected to a gating signal line configured for receiving a gating signal, the gating module is connected between the control terminal of the preset module and the control signal line, or between the first terminal of the preset module and the driving transistor, or between the second terminal of the preset module and the preset signal terminal or the driving transistor.

Abstract: A display panel and a display device are provided. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data-writing module, a driving module, and a compensation module. The data-writing module is configured to selectively provide a data signal for the driving module. The driving module includes a driving transistor and is configured to provide a driving current to the light-emitting element. The compensation module is configured to compensate a threshold voltage of the driving transistor. A source of the driving transistor includes a first source and a second source, and a drain of the driving transistor includes a first drain and a second drain. A third driving portion is arranged between the first source and the second source. A first driving portion is arranged between the second source and the first drain.

Abstract: A display panel includes a base substrate, a first transistor and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes an oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. The first transistor further includes a third gate electrode. Along the direction perpendicular to the base substrate, a distance between the third gate electrode and the first active layer is D3, and D1<D3.

Abstract: A display panel includes at least one driving circuit and at least one pixel circuit. A driving circuit of the at least one driving circuit provides a driving signal for a pixel circuit of the at least one pixel circuit. The driving circuit includes N-level shift registers cascaded with each other. N is greater than or equal to two. The pixel circuit provides a display signal for a display unit of the display panel. A shift register of the N-level shift registers includes at least one first transistor. The at least one first transistor includes at least one first active layer, and an active layer with a largest area among the at least one first active layer is a first preset active layer. The pixel circuit includes at least one second transistor. The at least one second transistor includes at least one second active layer.

Abstract: A display panel includes a base substrate, a third transistor and a fourth transistor. The third transistor and the fourth transistor are formed on the base substrate. The third transistor includes a sixth gate electrode, a third active layer, a third source electrode, and a third drain electrode. The third active layer includes an oxide semiconductor. The fourth transistor includes an eighth gate electrode, a fourth active layer, a fourth source electrode, and a fourth drain electrode. The fourth active layer includes another oxide semiconductor. Along a direction perpendicular to the base substrate, a distance between the sixth gate electrode and the third active layer is D6. A channel region of the third transistor defined by the sixth gate electrode is a sixth channel region. A length of the sixth channel region is L6. A sixth area S6=L6×D6.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module and a compensation module. The drive module includes a drive transistor. The data write module is connected to an input terminal of the drive module; a first electrode of the compensation module is connected to an output terminal of the drive module, and a second electrode of the compensation module is connected to a control terminal of the drive module. The data write module includes a data write transistor and a bias transistor, the data write transistor is connected to a data signal input terminal and configured to transmit a data signal, and the bias transistor is connected to a bias signal input terminal and configured to transmit a bias signal.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module, a compensation module and a reset module. The drive module includes a drive transistor. The data write module is connected between a data signal input terminal and a source of the drive transistor. The compensation module is connected between a gate of the drive transistor and the drain of the drive transistor. The rest module is connected between a reset signal terminal and the drain of the drive transistor. The reset module also serves as a bias module. An operation of the pixel circuit includes a reset stage and a bias stage, during the reset stage, the reset module and the compensation module are on.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module, a compensation module and a reset module. The drive module includes a drive transistor. The data write module is connected between a data signal input terminal and a source of the drive transistor. The compensation module is connected between a gate of the drive transistor and the drain of the drive transistor. The rest module is connected between a reset signal terminal and the drain of the drive transistor. The reset module also serves as a bias module. An operation of the pixel circuit includes a reset stage and a bias stage, during the reset stage, the reset module and the compensation module are on.