Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module, a compensation module and a reset module. The drive module includes a drive transistor. The data write module is connected between a data signal input terminal and a source of the drive transistor. The compensation module is connected between a gate of the drive transistor and the drain of the drive transistor. The rest module is connected between a reset signal terminal and the drain of the drive transistor. The reset module also serves as a bias module. An operation of the pixel circuit includes a reset stage and a bias stage, during the reset stage, the reset module and the compensation module are on.

Abstract: A display panel includes a base substrate, a first transistor, and a second transistor. The first transistor and the second transistor are formed on the base substrate. The first transistor includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes silicon. The second transistor includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode. The second active layer includes oxide semiconductor. A length of a channel region of the first transistor is L1. Along a direction perpendicular to the base substrate, a distance between the first gate electrode and the first active layer is D1. A length of a channel region of the second transistor is L2. Along the direction perpendicular to the base substrate, a distance between the second gate electrode and the second active layer is D2.

Abstract: Provided are a display panel an integrate chip and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a drive module and a data write module. The drive module is configured to provide a drive current for the light-emitting element and comprises a drive transistor. The data write module comprises a data write transistor and a bias transistor, the data write transistor is configured to transmit a data signal and the bias transistor is configured to transmit a bias signal.

Abstract: Disclosed are a banknote stacking and separation apparatus and a cash recycling and handling device. The banknote stacking and separation apparatus includes a frame provided with a banknote accommodating space. A pickuping roller, a feeding roller and a gate roller are provided in an upper part of the banknote accommodating space, and the feeding roller and the gate roller are oppositely arranged. The banknote stacking and separation apparatus further includes a guiding plate and a guiding plate driving mechanism. The guiding plate is located in the banknote accommodating space and pivoted with the frame, and the guiding plate driving mechanism drives the guiding plate to rotate from a guiding position to a lifting position. The guiding plate shields the pickuping roller when the guiding plate is at the guiding position, and the guiding plate exposes the pickuping roller when the guiding plate is at the lifting position.

Abstract: Provided are a cash box and a cash recycling and handling device. The cash box comprises a box body, a supporting plate and a self-locking assembly, where the self-locking assembly includes a stop plate disposed between a side wall of the box body and the supporting plate, and the stop plate is movably connected to the box body and has a lifted position and a lowered position; in a case where the stop plate is in the lifted position, the stop plate is in fit with the supporting plate to lock a position of the supporting plate; and in a case where the stop plate is in the lowered position, the stop plate is separated from the supporting plate to unlock the position of the supporting plate. The cash recycling and handling device includes at least one above-mentioned cash box.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a drive module and a data write module. The drive module is configured to provide a drive current for the light-emitting element and comprises a drive transistor. An operation of the pixel circuit includes a bias stage, in the bias stage, the data write module and the drive module are on, a compensation module is off, a data signal provides a bias signal for a drain of the drive transistor to adjust a bias state of the drive transistor.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module and a compensation module. The drive module includes a drive transistor. The data write module is connected to an input terminal of the drive module; a first electrode of the compensation module is connected to an output terminal of the drive module, and a second electrode of the compensation module is connected to a control terminal of the drive module. The data write module includes a data write transistor and a bias transistor, the data write transistor is connected to a data signal input terminal and configured to transmit a data signal, and the bias transistor is connected to a bias signal input terminal and configured to transmit a bias signal.

Abstract: Provided are a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element. The pixel circuit includes a data write module, a drive module and a compensation module. The drive module includes a drive transistor; the data write module is connected to an input terminal of the drive module, a first electrode of the compensation module is connected to an output terminal of the drive module, and a second electrode of the compensation module is connected to a control terminal of the drive module. The data write module includes a data write transistor and a bias transistor, the data write transistor is connected to a data signal input terminal and configured to transmit a data signal, and the bias transistor is connected to a bias signal input terminal and configured to transmit a bias signal.

Abstract: Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded; wherein the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control comprising a first capacitor and a first transistor, wherein a second plate of the first capacitor is connected to a drain of the first transistor, a source of the first transistor receives a first control signal, and a gate of the first transistor receives a second control signal.

Abstract: A display panel and a display device are provided. The display panel includes at least one driving circuit and at least one pixel circuit. A driving circuit provides a driving signal for a pixel circuit. The driving circuit includes N-level shift registers cascaded with each other, where N is greater than or equal to two. A shift register includes at least one first active layer, and an active layer with a largest area is a first preset active layer. The pixel circuit includes at least one second active layer, where an active layer with a largest area among active layers containing silicon is a second preset active layer, and an active layer with a largest area among active layers containing oxide semiconductor is a third preset active layer. The first preset active layer has an area greater than the second preset active layer and the third preset active layer.

Abstract: Provided are a display panel and display device. The display panel includes a driver circuit comprising a shift register that is N-stage cascaded; wherein the shift register comprises: a third control unit configured to receive a first voltage signal and generate an output signal in response to a signal of a third node, or receive a second voltage signal and generate an output signal in response to a signal of a second node; and a fourth control comprising a first capacitor and a first transistor, wherein a second plate of the first capacitor is connected to a drain of the first transistor, a first plate of the first capacitor and a gate of the first transistor are connected to a same node; and/or a first plate of the first capacitor and a gate of the first transistor receive a same signal.

Abstract: A display panel and a display device are provided in the present disclosure. The display panel includes a base substrate, a first transistor, a second transistor, a pixel circuit, and a drive circuit. A first active layer of the first transistor includes silicon; and a second active layer of the second transistor includes an oxide semiconductor. A length of a channel region of the first transistor is LL a distance between a first gate electrode and the first active layer is D1, and a first area S1=L1×D1; and a length of a channel region of the second transistor is L2, a distance between a second gate electrode and the second active layer is D2, and a second area S2=L2×D2, where S1<S2. The second transistor is included in the drive circuit, and the first transistor is included in one of the pixel circuit and the drive circuit.

Abstract: The application provides a display panel, integrated chip component and display device. The display panel includes: a first display area and a second display area; pixel circuits comprising first pixel circuits and second pixel circuits, the first pixel circuits and the second pixel circuits being configured to provide driving currents for light-emitting elements in the first display area and the second display area, respectively; and first pixel units and second pixel units, each first pixel unit comprising a first pixel circuit and a light-emitting element connected to the first pixel circuit, and each second pixel unit comprising a second pixel circuit and a light-emitting element connected to the second pixel circuit; wherein each first pixel unit is configured to receive a first power supply signal V1 and a second power supply signal V2, V1>V2.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. A shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit comprises a first gating unit. One terminal of the first gating unit is connected to a preset node, another terminal of the first gating unit is connected to a fourth node, and a control terminal of the first gating unit is configured to receive a fifth voltage signal. The second control unit is configured to receive at least a third voltage signal and a signal of the fourth node or receive at least a fourth voltage signal and a signal of a fifth node and generate an output signal.

Abstract: Provided are a display panel and a display device. The display panel includes a driver circuit including N stages of cascaded shift registers, where N?2. A shift register includes a first control part and a second control part. The second control part includes a first control unit and a second control unit. The first control unit is configured to receive at least a signal of a preset node and a first output control signal and control a signal of a fourth node. During at least part of a time period during which the signal of the fourth node is a low level signal, each of a signal of the preset node and the first output control signal is a low level signal.

Abstract: Display device and driving method thereof are provided. The display device includes a housing, a display screen, and a drive circuit. The housing includes a first side and a second side opposite to the first side in a first direction. The display screen includes a first end and a second end. At least one of the first end and the second end is accommodated in the housing. A first display area in a display area of the display screen is located between the first side and the second side. A second display area in the display area of the display screen is accommodated in the housing. The drive circuit is configured, when the display screen displays an image, to provide drive signals to the first display area, and control a display of the first display area without providing the drive signals to the second display area.

Abstract: Disclosed are a sheet-type medium conveying device and a cash recycling and handling apparatus. The sheet-type medium conveying device includes a first passage plate, a second passage plate and a driving mechanism. The first passage plate and the second passage plate are oppositely arranged. A passage is formed between the first passage plate and the second passage plate, and configured for a sheet-type medium to pass through. The driving mechanism is configured to drive a first end of the first passage plate and a first end of the second passage plate to get close to or away from each other.

Abstract: A display panel includes a shift register, a pixel circuit, and a driving circuit. The shift register includes a first control unit, a second control unit, a third control unit, and a fourth control unit. The first control unit is configured to receive an input signal and control a signal of a first node in response to a first clock signal. The second control unit is configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node.

Abstract: A display panel includes a driving circuit. The driving circuit includes N levels of shift registers cascaded with each other, N?2. A shift register of the N levels of the shift registers includes a third control unit and a fourth control unit. The third control unit is configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node. The first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The fourth control unit is configured to receive a third voltage signal and a fourth voltage signal and generate an output signal in response to the signal of the first node and the signal of the fourth node and includes a first transistor and a second transistor.

Abstract: A display panel includes a pixel circuit and a driving circuit. The pixel circuit includes a driving transistor. The driving circuit is configured to provide a signal for the pixel circuit, receive a third voltage signal and a fourth voltage signal, and generate an output signal. The third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal. A working process of the pixel circuit includes a reset phase and a bias phase. The output signal of the driving circuit is a reset signal in the reset phase. The output signal of the driving circuit is a bias signal in the bias phase. In response to the driving transistor being a PMOS transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal.