Abstract: A combination structure of semiconductor deep trench devices includes: a deep trench insulator device, which includes at least one deep trench ring unit, wherein the deep trench ring unit includes: a deep trench ring, a first dielectric side wall layer and a first poly silicon fill region; and a deep trench capacitor device, which includes a plurality of deep trench capacitor units and a cathode, wherein each of the deep trench capacitor units includes: a deep trench hole; a second dielectric side wall layer; and a second poly silicon fill region. The deep trench hole is formed by etching a semiconductor substrate with a same etch process step with the deep trench ring. The first dielectric side wall layer and the second dielectric side wall layer is formed by a same oxide growth process step.

Abstract: Disclosed in the present invention a cold rolled steel plate for a galvanized steel plate, containing Fe and inevitable impurities, and also containing the following chemical elements, in mass percent: 0.18-0.25% of C, 1.5-2.0% of Si, 1.5-2.3% of Mn, and 0.01-0.06% of Nb. The microstructure of the cold rolled steel plate is bainite+tempered martensite+residual austenite, wherein the volume fraction of bainite and tempered martensite is great than or equal to 95%. Accordingly, also disclosed in the present invention is a manufacturing method for the galvanized steel plate, comprising the steps: (1) smelting and casting to obtain a steel billet; (2) hot rolling; (3) cold rolling; (4) annealing: the annealing soaking temperature is 890-920° C., the soaking and heat preservation time is 80-150 s, and then cooling is performed at a cooling rate of 30-100° C./s to reach 270-350° C.; (5) overaging: the overaging temperature is 450-475° C.

Abstract: A method includes: generating first specification data of a semiconductor device; performing, to the first specification data, a first evaluation operation corresponding to a first physical feature to the first specification data, to generate first parameters; performing, to the first specification data, a second evaluation operation corresponding to a second physical feature different from the first physical feature, to generate second parameters; comparing the first parameters and the second parameters with preset parameters; and when the first parameters and the second parameters meet the preset parameters, manufacturing the semiconductor device according to the first specification data.

Abstract: A depletion type vertical discrete NMOS device includes: an N-type epitaxial layer formed on an N-type substrate, wherein the N-type epitaxial layer has a top surface and a bottom surface opposite to each other; a P-type well formed in the N-type epitaxial layer; a gate formed outside and connected with the N-type epitaxial layer; an N-type source formed in the N-type epitaxial layer and in contact with the P-type well; an N-type drain including a part of the N-type substrate, which is formed outside and under the N-type epitaxial layer; and an N-type region formed and connected between the P-type well and the gate, which provides a channel, such that the N-type source and the N-type drain are electrically connected with each other during conduction operation, whereas, the N-type source and the N-type drain are electrically disconnected from each other during non-conduction operation.

Abstract: A chip package unit includes: a base material; at least one chip, disposed on the base material; a package material, enclosing the base material and the chip; and at least one heat dissipation paste curing layer, formed by curing the heat dissipation paste, on a top side of the package material or a back side of the chip in a printed pattern.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: Disclosed in the present invention are TRIP steel and a preparation method therefor, a cold-rolled steel sheet, and a hot-dip galvanized steel sheet, wherein the TRIP steel comprises the following chemical components, in percentages by mass: C: 0.15-0.3%, Si: 0.6-1.0%, Mn: 1.7-2.5%, Al: 0.5-0.9%, P?0.01%, S?0.01%, N?0.007%, and Fe?90%. The TRIP steel of the present invention is based on carbon-silicon-manganese steel. By means of optimizing the proportions of carbon, silicon, manganese and aluminum, and replacing Si in traditional TRIP steel with a part of the Al, the effects of inhibiting carbide precipitation and stabilizing residual austenite can be achieved so as to ensure the mechanical properties of the TRIP steel, and the surface quality and plateability of the steel sheet can also be improved.

Abstract: Disclosed is a pressure cooker having a negative pressure vacuum state, including a body having an accommodating space, a cover, and a control structure. The control structure includes a sealing elastic member, a pressure relief valve, and a stop valve. The accommodating space includes a high pressure state, a micro-positive pressure state, and a negative pressure vacuum state, and when the accommodating space is in the high pressure state, the pressure relief valve is lifted upward by a high pressure thrust, to discharge high pressure gas in the accommodating space, and the stop valve is lifted upward under pressure to limit opening of the cover and is in a sealed state; and when the accommodating space is in the micro-positive pressure state or the negative pressure vacuum state, the pressure relief valve, the stop valve, the body, and the cover each are in the sealed state.

Abstract: Provided are a manufacturing method for a hot-dip galvanized steel plate, and the hot-dip galvanized steel plate. The method comprises: hot rolling a slab into a steel plate, and pickling and cold rolling after coiling; performing continuous annealing, an annealing temperature being 840-870° C., and an annealing dew point being ?10-0° C.; cooling to 710-730° C. at a cooling rate of ?10° C./s, and then cooling to 220-320° C. at a cooling speed of ?50° C./s; then heating to 410-460° C. for heat preservation for 20-100 s; and galvanization to obtain the hot-dip galvanized steel plate, the chemical element composition thereof being: C: 0.17-0.21 wt %; Si: 1.2-1.7 wt %; Al: 0.02-0.05%; Mn: 1.60-2.1 wt %; N: ?0.008 wt %; and the reminder being Fe and impurities. The hot-dip galvanized steel plate of the present invention has a yield strength of 400-600 Mpa, a tensile strength of 730-900 Mpa, an elongation of 25-35%, and a hole expansion ratio of 35-60%.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

Abstract: A lead frame includes: a die pad having a die disposing area; a plurality of lead pads located around the die pad; an outer frame, located at a periphery of the die pad and the lead pads; and at least two tie bars, respectively connected between the outer frame and two opposite sides of the die pad. At least one of the die pad and the tie bars includes a thermal deformation mitigation structure.

Abstract: Disclosed are a stress-resistant, creep-resistant, high-temperature resistant and high-insulation sheath material for a maglev train cable, and a manufacturing method and use thereof. A multiple chemical crosslinking structure is constructed by blending a functional polyvinylsilicone grease with ultra-high molecular weight polyethylene (UHMWPE) and a ceramicized silicone rubber as a cable material matrix and using electron beam irradiation. In addition, organic/inorganic fillers in the matrix can form physical crosslinking points in the material. A physical-chemical dual crosslinking structure is constructed in the matrix, which can limit the motion and relaxation of molecular chains and improve the interaction between the insulation layer and sheath layer and refractory layers such as fillers and mica tapes to avoid the relative displacement during the laying and operation and improve the high-temperature resistance, creep resistance and stress relaxation resistance of a UHMWPE cable sheath material.

Abstract: An antenna device includes an insulating carrier and a first primary antenna having a first feeding-in section, a first auxiliary antenna having a second feeding-in section and a second grounding section, a second primary antenna having a third feeding-in section, a second auxiliary antenna having a fourth feeding-in section and a grounding face which are provided on a face of the carrier. The first primary and auxiliary antennas and the second primary and auxiliary antennas are positioned at two side edges of the carrier which are away from each other. The grounding face is positioned between both the first primary and auxiliary antennas and the second primary and auxiliary antennas. The grounding face is provided with a first grounding section adjacent to the first feeding-in section, a third grounding section adjacent to third feeding-in section and a fourth grounding section adjacent to the fourth feeding-in section.

Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.

Abstract: A native NMOS device includes: a P-type epitaxial layer, a first and a second insulation region, a first P-type well, a second P-type well, a gate, an N-type source, and an N-type drain. The P-type epitaxial layer has a first concentration of P-type doped impurities. The first P-type well completely encompasses and is in contact with a lower surface of the N-type source. The second P-type well completely encompasses and is in contact with a lower surface of the N-type drain. Each of the first P-type well and the second P-type well has a second concentration of P-type doped impurities, and the second concentration of P-type doped impurities is higher than the first concentration of P-type doped impurities. The second concentration of P-type doped impurities is sufficient for preventing a leakage current from flowing between the N-type drain and the P-type substrate while the native NMOS device is in operation.

Abstract: Disclosed are a stress-resistant, creep-resistant, high-temperature resistant and high-insulation sheath material for a maglev train cable, and a manufacturing method and use thereof. A multiple chemical crosslinking structure is constructed by blending a functional polyvinylsilicone grease with ultra-high molecular weight polyethylene (UHMWPE) and a ceramicized silicone rubber as a cable material matrix and using electron beam irradiation. In addition, organic/inorganic fillers in the matrix can form physical crosslinking points in the material. A physical-chemical dual crosslinking structure is constructed in the matrix, which can limit the motion and relaxation of molecular chains and improve the interaction between the insulation layer and sheath layer and refractory layers such as fillers and mica tapes to avoid the relative displacement during the laying and operation and improve the high-temperature resistance, creep resistance and stress relaxation resistance of a UHMWPE cable sheath material.

Abstract: An integrated structure of semiconductor devices having a shared contact plug includes: a first device, a second device and a shared contact plug. The first device includes a first gate having a conduction region, two spacer regions and a protection region. The two spacer regions overlay and are connected with two ends of the conductive region, respectively. The protection region overlays and is connected with the spacer region located outside a shared side of the conductive region. The second device includes a shared region, wherein the shared region is located in a semiconductor layer which is located below and outside the protection region. The shared contact plug is formed on and in contact with the conductive region and the shared region. The first gate is electrically connected with the shared region through the shared contact plug, wherein the shared contact plug overlays and is connected with the protection region.

Abstract: A semiconductor device with a pad structure resistant to plasma damage includes: a main pad portion including main conductor units and main via units; a sub-pad portion including sub-conductor units and sub-via units; a pad bonding unit in direct contact with and in connection with a top main conductor unit, wherein the top main conductor unit is the main conductor unit formed in a top metal layer; and a bridge pad unit in direct contact with a top sub-conductor unit, wherein the top sub-conductor unit is the sub-conductor unit formed in the top metal layer. The bridge pad unit is in direct contact with the pad bonding unit. The main pad portion and sub-pad portion are located below the pad bonding unit and bridge pad unit respectively, and the main pad portion and the sub-pad portion are not in direct connection with each other.