Patents by Inventor Yong Zhong

Yong Zhong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250140630
    Abstract: A chip package unit includes: a base material; at least one chip, disposed on the base material; a package material, enclosing the base material and the chip; and at least one heat dissipation paste curing layer, formed by curing the heat dissipation paste, on a top side of the package material or a back side of the chip in a printed pattern.
    Type: Application
    Filed: January 4, 2025
    Publication date: May 1, 2025
    Inventors: Hao-Lin Yen, Heng-Chi Huang, Yong-Zhong Hu
  • Publication number: 20250142873
    Abstract: A depletion type vertical discrete NMOS device includes: an N-type epitaxial layer formed on an N-type substrate, wherein the N-type epitaxial layer has a top surface and a bottom surface opposite to each other; a P-type well formed in the N-type epitaxial layer; a gate formed outside and connected with the N-type epitaxial layer; an N-type source formed in the N-type epitaxial layer and in contact with the P-type well; an N-type drain including a part of the N-type substrate, which is formed outside and under the N-type epitaxial layer; and an N-type region formed and connected between the P-type well and the gate, which provides a channel, such that the N-type source and the N-type drain are electrically connected with each other during conduction operation, whereas, the N-type source and the N-type drain are electrically disconnected from each other during non-conduction operation.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 1, 2025
    Inventors: Wu-Te Weng, Yi-Rong Tu, Ying-Shiou Lin, Yong-Zhong Hu
  • Patent number: 12272592
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: April 8, 2025
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20240297067
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Application
    Filed: May 15, 2024
    Publication date: September 5, 2024
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20240287660
    Abstract: Disclosed in the present invention are TRIP steel and a preparation method therefor, a cold-rolled steel sheet, and a hot-dip galvanized steel sheet, wherein the TRIP steel comprises the following chemical components, in percentages by mass: C: 0.15-0.3%, Si: 0.6-1.0%, Mn: 1.7-2.5%, Al: 0.5-0.9%, P?0.01%, S?0.01%, N?0.007%, and Fe?90%. The TRIP steel of the present invention is based on carbon-silicon-manganese steel. By means of optimizing the proportions of carbon, silicon, manganese and aluminum, and replacing Si in traditional TRIP steel with a part of the Al, the effects of inhibiting carbide precipitation and stabilizing residual austenite can be achieved so as to ensure the mechanical properties of the TRIP steel, and the surface quality and plateability of the steel sheet can also be improved.
    Type: Application
    Filed: June 29, 2022
    Publication date: August 29, 2024
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Mengxiao CHEN, Yong ZHONG, Li WANG, Shuang XIE
  • Publication number: 20240277177
    Abstract: Disclosed is a pressure cooker having a negative pressure vacuum state, including a body having an accommodating space, a cover, and a control structure. The control structure includes a sealing elastic member, a pressure relief valve, and a stop valve. The accommodating space includes a high pressure state, a micro-positive pressure state, and a negative pressure vacuum state, and when the accommodating space is in the high pressure state, the pressure relief valve is lifted upward by a high pressure thrust, to discharge high pressure gas in the accommodating space, and the stop valve is lifted upward under pressure to limit opening of the cover and is in a sealed state; and when the accommodating space is in the micro-positive pressure state or the negative pressure vacuum state, the pressure relief valve, the stop valve, the body, and the cover each are in the sealed state.
    Type: Application
    Filed: November 23, 2021
    Publication date: August 22, 2024
    Inventors: Kunrong Ji, Xiaoxing Shen, Yong Zhong, Anmin Liu
  • Publication number: 20240271257
    Abstract: Provided are a manufacturing method for a hot-dip galvanized steel plate, and the hot-dip galvanized steel plate. The method comprises: hot rolling a slab into a steel plate, and pickling and cold rolling after coiling; performing continuous annealing, an annealing temperature being 840-870° C., and an annealing dew point being ?10-0° C.; cooling to 710-730° C. at a cooling rate of ?10° C./s, and then cooling to 220-320° C. at a cooling speed of ?50° C./s; then heating to 410-460° C. for heat preservation for 20-100 s; and galvanization to obtain the hot-dip galvanized steel plate, the chemical element composition thereof being: C: 0.17-0.21 wt %; Si: 1.2-1.7 wt %; Al: 0.02-0.05%; Mn: 1.60-2.1 wt %; N: ?0.008 wt %; and the reminder being Fe and impurities. The hot-dip galvanized steel plate of the present invention has a yield strength of 400-600 Mpa, a tensile strength of 730-900 Mpa, an elongation of 25-35%, and a hole expansion ratio of 35-60%.
    Type: Application
    Filed: June 7, 2022
    Publication date: August 15, 2024
    Applicant: BAOSHAN IRON & STEEL CO., LTD.
    Inventors: Yong ZHONG, Mengxiao CHEN, Li WANG
  • Patent number: 12062570
    Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: August 13, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
  • Publication number: 20240234264
    Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 11, 2024
    Inventors: Hao-Lin Yen, Heng-Chi Huang, Yong-Zhong Hu
  • Publication number: 20240203840
    Abstract: A lead frame includes: a die pad having a die disposing area; a plurality of lead pads located around the die pad; an outer frame, located at a periphery of the die pad and the lead pads; and at least two tie bars, respectively connected between the outer frame and two opposite sides of the die pad. At least one of the die pad and the tie bars includes a thermal deformation mitigation structure.
    Type: Application
    Filed: November 28, 2023
    Publication date: June 20, 2024
    Inventors: Shih-Chieh Lin, Min-Shun Lo, Heng-Chi Huang, Yong-Zhong Hu
  • Patent number: 12002601
    Abstract: Disclosed are a stress-resistant, creep-resistant, high-temperature resistant and high-insulation sheath material for a maglev train cable, and a manufacturing method and use thereof. A multiple chemical crosslinking structure is constructed by blending a functional polyvinylsilicone grease with ultra-high molecular weight polyethylene (UHMWPE) and a ceramicized silicone rubber as a cable material matrix and using electron beam irradiation. In addition, organic/inorganic fillers in the matrix can form physical crosslinking points in the material. A physical-chemical dual crosslinking structure is constructed in the matrix, which can limit the motion and relaxation of molecular chains and improve the interaction between the insulation layer and sheath layer and refractory layers such as fillers and mica tapes to avoid the relative displacement during the laying and operation and improve the high-temperature resistance, creep resistance and stress relaxation resistance of a UHMWPE cable sheath material.
    Type: Grant
    Filed: October 27, 2023
    Date of Patent: June 4, 2024
    Assignee: Anhui Jianzhu University
    Inventors: Ping Wang, Shang Gao, Yong Zhong, Wenxiu Liu, Tao Hong, Tao Song, Long Chen, Bin Ye, Yunsheng Ding, Li Yang, Jie Song, Hongyu Tian, Haibing Lu
  • Patent number: 11996620
    Abstract: An antenna device includes an insulating carrier and a first primary antenna having a first feeding-in section, a first auxiliary antenna having a second feeding-in section and a second grounding section, a second primary antenna having a third feeding-in section, a second auxiliary antenna having a fourth feeding-in section and a grounding face which are provided on a face of the carrier. The first primary and auxiliary antennas and the second primary and auxiliary antennas are positioned at two side edges of the carrier which are away from each other. The grounding face is positioned between both the first primary and auxiliary antennas and the second primary and auxiliary antennas. The grounding face is provided with a first grounding section adjacent to the first feeding-in section, a third grounding section adjacent to third feeding-in section and a fourth grounding section adjacent to the fourth feeding-in section.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: May 28, 2024
    Assignee: Molex, LLC
    Inventors: Ping Zhang, Guang Yong Zhong, Xue Tian Zhao, Chun Xia Zhang, Hai Liu, Kang Cheng, Qian Gao
  • Patent number: 11973010
    Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 30, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hao-Lin Yen, Heng-Chi Huang, Yong-Zhong Hu
  • Publication number: 20240105844
    Abstract: A native NMOS device includes: a P-type epitaxial layer, a first and a second insulation region, a first P-type well, a second P-type well, a gate, an N-type source, and an N-type drain. The P-type epitaxial layer has a first concentration of P-type doped impurities. The first P-type well completely encompasses and is in contact with a lower surface of the N-type source. The second P-type well completely encompasses and is in contact with a lower surface of the N-type drain. Each of the first P-type well and the second P-type well has a second concentration of P-type doped impurities, and the second concentration of P-type doped impurities is higher than the first concentration of P-type doped impurities. The second concentration of P-type doped impurities is sufficient for preventing a leakage current from flowing between the N-type drain and the P-type substrate while the native NMOS device is in operation.
    Type: Application
    Filed: September 7, 2023
    Publication date: March 28, 2024
    Inventors: Ying-Shiou Lin, Wu-Te Weng, Yong-Zhong Hu
  • Publication number: 20240062935
    Abstract: Disclosed are a stress-resistant, creep-resistant, high-temperature resistant and high-insulation sheath material for a maglev train cable, and a manufacturing method and use thereof. A multiple chemical crosslinking structure is constructed by blending a functional polyvinylsilicone grease with ultra-high molecular weight polyethylene (UHMWPE) and a ceramicized silicone rubber as a cable material matrix and using electron beam irradiation. In addition, organic/inorganic fillers in the matrix can form physical crosslinking points in the material. A physical-chemical dual crosslinking structure is constructed in the matrix, which can limit the motion and relaxation of molecular chains and improve the interaction between the insulation layer and sheath layer and refractory layers such as fillers and mica tapes to avoid the relative displacement during the laying and operation and improve the high-temperature resistance, creep resistance and stress relaxation resistance of a UHMWPE cable sheath material.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 22, 2024
    Applicant: Anhui Jianzhu University
    Inventors: Ping WANG, Shang GAO, Yong ZHONG, Wenxiu LIU, Tao HONG, Tao SONG, Long CHEN, Bin YE, Yunsheng DING, Li YANG, Jie SONG, Hongyu TIAN, Haibing LU
  • Publication number: 20240030297
    Abstract: An integrated structure of semiconductor devices having a shared contact plug includes: a first device, a second device and a shared contact plug. The first device includes a first gate having a conduction region, two spacer regions and a protection region. The two spacer regions overlay and are connected with two ends of the conductive region, respectively. The protection region overlays and is connected with the spacer region located outside a shared side of the conductive region. The second device includes a shared region, wherein the shared region is located in a semiconductor layer which is located below and outside the protection region. The shared contact plug is formed on and in contact with the conductive region and the shared region. The first gate is electrically connected with the shared region through the shared contact plug, wherein the shared contact plug overlays and is connected with the protection region.
    Type: Application
    Filed: May 9, 2023
    Publication date: January 25, 2024
    Inventors: Chin-Chin Tsai, Han-Chung Tai, Yong-Zhong Hu
  • Publication number: 20240014154
    Abstract: A semiconductor device with a pad structure resistant to plasma damage includes: a main pad portion including main conductor units and main via units; a sub-pad portion including sub-conductor units and sub-via units; a pad bonding unit in direct contact with and in connection with a top main conductor unit, wherein the top main conductor unit is the main conductor unit formed in a top metal layer; and a bridge pad unit in direct contact with a top sub-conductor unit, wherein the top sub-conductor unit is the sub-conductor unit formed in the top metal layer. The bridge pad unit is in direct contact with the pad bonding unit. The main pad portion and sub-pad portion are located below the pad bonding unit and bridge pad unit respectively, and the main pad portion and the sub-pad portion are not in direct connection with each other.
    Type: Application
    Filed: March 21, 2023
    Publication date: January 11, 2024
    Inventors: Wu-Te WENG, Yong-Zhong HU
  • Publication number: 20230397755
    Abstract: Methods and systems for employing a sensor to detect disconnection of a liquid supply tank and a low fill level of the liquid supply tank are disclosed herein. The sensor may have a conductive probe to contact liquid, e.g., to detect a liquid level in a removable liquid supply tank.
    Type: Application
    Filed: October 26, 2021
    Publication date: December 14, 2023
    Applicant: Keurig Green Mountain, Inc.
    Inventors: Chang Geng, Fa Yong Zhong, Cong Xing Ma, Zheng Xu
  • Publication number: 20230335916
    Abstract: An antenna device is provided to include an antenna radiating assembly, the antenna radiating assembly includes: a first metal plate; at least two antennas including a first mobile communication antenna and a second mobile communication antenna, the first mobile communication antenna and the second mobile communication antenna are respectively perpendicularly provided to a surface of the first metal plate, and the first mobile communication antenna and the second mobile communication antenna are perpendicular to each other; a second metal plate extending from a side of the first metal plate toward the first mobile communication antenna and the second mobile communication antenna. So a small dimension antenna device is provided to consider an antenna dimension and antenna performance at the same time, employ a three-dimensional antenna structure to reduce the dimension, at the same time assure isolation degree between two mobile communication antennas and promote antenna performance.
    Type: Application
    Filed: April 10, 2023
    Publication date: October 19, 2023
    Inventors: Ping Zhang, Guang-Yong Zhong, Hai Liu, Chun-Xia Zhang
  • Publication number: 20230299482
    Abstract: An antenna device includes: a dielectric substrate; a first grounding face, a second grounding face and a third grounding face which are provided on a first face of the dielectric substrate and are isolated from each other; a first primary antenna and a first auxiliary antenna which are provided on the first face, cooperatively act with the first grounding face to operate at a first frequency range and are isolated from each other; a second primary antenna and a second auxiliary antenna which cooperatively act with the first grounding face to operate at a second frequency range and are isolated from each other; a third primary antenna which cooperatively acts with the second grounding face to operate at a third frequency range; and a third auxiliary antenna which cooperatively acts with the third grounding face to operate at the third frequency range.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 21, 2023
    Inventors: Hai Liu, Guang-Yong Zhong, Ping Zhang, Chun-Xia Zhang, Kang Cheng