Abstract: Embodiments of the present disclosure generally relate to processing a workpiece containing a substrate during deposition, etching, and/or curing processes with a mask to have localized deposition on the workpiece. A mask is placed on a first layer of a workpiece, which protects a plurality of trenches from deposition of a second layer. In some embodiments, the mask is placed before deposition of the second layer. In other embodiments, the second layer is cured before the mask is deposited. In other embodiments, the second layer is etched after the mask is deposited. Methods disclosed herein allow the deposition of a second layer in some of the trenches present in the workpiece, while at least partially preventing deposition of the second layer in other trenches present in the workpiece.

Abstract: Embodiments of the invention include methods and structures for controlling developer critical dimension (DCD) variations across a wafer surface. Aspects of the invention include an apparatus having developer tubing and an internal cam. The internal cam is coupled to a fixed axis. A flexible divider is positioned between the developer tubing and the internal cam. The flexible divider is coupled to the internal cam such that rotation of the internal cam about the fixed axis is operable to change an inner diameter of the developer tubing.

Abstract: Embodiments of the present disclosure include a die system and a method of comparing alignment vectors. The die system includes a plurality of dies arranged in a desired pattern. An alignment vector, such as a die vector, can be determined from edge features of the die. The alignment vectors can be compared to other dies or die patterns in the same system. A method of comparing dies and die patterns includes comparing die vectors and/or pattern vectors. The comparison between alignment vectors allows for fixing the die patterns for the next round of processing. The methods provided allow accurate comparisons between as-deposited edge features, such that accurate stitching of dies can be achieved.

Abstract: A method and apparatus for determining a line angle and a line angle rotation of a grating or line feature is disclosed. An aspect of the present disclosure involves, measuring coordinate points of a first line feature using a measurement tool, determining a first slope of the first line feature from the coordinate points, and determining a first line angle from the slope of the first line feature. This process can be repeated to find a second slope of a second line feature that is adjacent to the first line feature. The slope of the first and second line features can be compared to find a line angle rotation. The line angle rotation is compared to a design specification and a stitch quality is determined.

Abstract: A method of making a semiconductor device includes depositing an oxide material on a patterned mask arranged on a substrate. The method further includes removing a portion of the oxide material such that the patterned mask is exposed. The method also includes removing the patterned mask such that the substrate is exposed between areas of remaining oxide material.

Abstract: A method of imprinting a pattern on a substrate is provided. The method includes forming a first pattern on a plurality of masters using a method other than imprinting, the first pattern including a plurality of patterned features of varying sizes; measuring the patterned features at a plurality of locations on each of the masters; selecting a first master of the plurality of masters based on the measurements of the patterned features on each of the masters; using the first master to form a second pattern on an imprint template; and imprinting the first pattern on a first device with the imprint template.

Abstract: An image projection system is provided. The system can be used for performing lithography. The system includes a deuterium light source, a converging lens coupled to the deuterium light source. The system includes an aperture configured to provide image tiling disposed adjacent to the converging lens. The system includes a movable stage disposed adjacent to the aperture. A method of fabricating an optical device is provided. The method includes depositing a resist over a substrate and determining an exposure pattern for the optical device. The method includes exposing a portion of the resist with a light beam based on the determined exposure pattern. Exposing the portion of the resist includes directing the light beam from a deuterium light source to the substrate and developing the resist.

Abstract: Methods of fabricating large-scale optical devices having sub-micron dimensions are provided. A method is provided that includes projecting a beam to a mask, the mask corresponding to a section of an optical device pattern, the optical device pattern divided into four or more equal portions, each portion corresponding to a section of a substrate. The method further includes scanning the mask over a first section of the substrate to pattern a first portion of the optical device pattern, the substrate is positioned at a first rotation angle relative to the mask. The method further includes rotating the substrate to a second rotation angle, the second rotation angle corresponding to 360° divided by a total number of portions of the optical device pattern, scanning the mask over a second section of the substrate from the initial position to the final position to pattern a second portion of the optical device pattern.

Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Abstract: A method of forming a BEOL interconnect structure having improved resistance-capacitance is provided in which a via metal layer is created by a first metallization process and thereafter shrunk by a subtractive etch; these steps relax the critical dimension, ensure a via straight profile, avoid via chamfering and bowing, and maximize metal volume. Top trench metallization is then performed above the via metal layer; this step eliminates reactive ion etch lag and ensures no metallization void issues.

Abstract: The present disclosure generally relates to methods of forming optical devices comprising nanostructures disposed on transparent substrates. A first process of forming the nanostructures comprises depositing a first layer of a first material on a glass substrate, forming one or more trenches in the first layer, and depositing a second layer of a second material in the one or more holes to trenches a first alternating layer of alternating first portions of the first material and second portions of the second material. The first process is repeated one or more times to form additional alternating layers over the first alternating layer. Each first portion of each alternating layer is disposed in contact with and offset a distance from an adjacent first portion in adjacent alternating layers. A second process comprises removing either the first or the second portions from each alternating layer to form the plurality of nanostructures.

Abstract: A method of forming patterned features on a substrate is provided. The method includes positioning a plurality of masks arranged in a mask layout over a substrate. The substrate is positioned in a first plane and the plurality of masks are positioned in a second plane, the plurality of masks in the mask layout have edges that each extend parallel to the first plane and parallel or perpendicular to an alignment feature on the substrate, the substrate includes a plurality of areas configured to be patterned by energy directed through the masks arranged in the mask layout. The method further includes directing energy towards the plurality of areas through the plurality of masks arranged in the mask layout over the substrate to form a plurality of patterned features in each of the plurality of areas.

Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Abstract: A method includes applying a first metallic layer having a first metallic material onto a substrate of a semiconductor component. The method further includes removing portions of the first metallic layer to form a first metallic line. The method further includes creating an opening in the first metallic line. The method also includes depositing a dielectric material on the substrate. The method further includes forming at least one trench in the dielectric material. The method also includes depositing a second metallic material within the at least one trench to form a second metallic line. At least the first and second metallic lines and the dielectric material form an interconnect structure of the semiconductor component.

Abstract: A method of forming a BEOL interconnect structure having improved resistance-capacitance is provided in which a via metal layer is created by a first metallization process and thereafter shrunk by a subtractive etch; these steps relax the critical dimension, ensure a via straight profile, avoid via chamfering and bowing, and maximize metal volume. Top trench metallization is then performed above the via metal layer; this step eliminates reactive ion etch lag and ensures no metallization void issues.

Abstract: Embodiments of the present disclosure relate to methods for positioning masks in a propagation direction of a light source. The masks correspond to a pattern to be written into a photoresist layer of a substrate. The masks are positioned by stitching a first mask and a second mask. The first mask includes a set of first features having first feature extensions extending therefrom at first feature interfaces. The second mask includes a set of second features having second feature extensions extending therefrom at second feature interfaces. Each first feature extension stitches with each corresponding second feature extension to form each stitched portion of a first stitched portion of the first pair of masks. The stitched portion of the first pair of masks defines a portion of the pattern to be written into the photoresist layer.

Abstract: A method of forming patterned features on a substrate is provided. The method includes positioning a plurality of masks arranged in a mask layout over a substrate. The substrate is positioned in a first plane and the plurality of masks are positioned in a second plane, the plurality of masks in the mask layout have edges that each extend parallel to the first plane and parallel or perpendicular to an alignment feature on the substrate, the substrate includes a plurality of areas configured to be patterned by energy directed through the masks arranged in the mask layout. The method further includes directing energy towards the plurality of areas through the plurality of masks arranged in the mask layout over the substrate to form a plurality of patterned features in each of the plurality of areas.

Abstract: A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

Abstract: Aspects of the present disclosure relate generally to methods and apparatus of processing transparent substrates, such as glass substrates. In one implementation, a film stack for optical devices includes a glass substrate including a first surface and a second surface. The film stack includes a device function layer formed on the first surface, a hard mask layer formed on the device function layer, and a substrate recognition layer formed on the hard mask layer. The hard mask layer includes one or more of chromium, ruthenium, or titanium nitride. The film stack includes a backside layer formed on the second surface. The backside layer formed on the second surface includes one or more of a conductive layer or an oxide layer.

Abstract: A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.