Patents by Inventor Yonggang Li

Yonggang Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220093520
    Abstract: Conductive routes for an electronic substrate may be fabricated by forming an opening in a material, using existing laser drilling or lithography tools and materials, followed by selectively plating a metal on the sidewalls of the opening. The processes of the present description may result in significantly higher patterning resolution or feature scaling (up to 2× improvement in patterning density/resolution). In addition to improved patterning resolution, the embodiments of the present description may also result in higher aspect ratios of the conductive routes, which can result in improved signaling, reduced latency, and improved yield.
    Type: Application
    Filed: September 21, 2020
    Publication date: March 24, 2022
    Applicant: Intel Corporation
    Inventors: Jeremy D. Ecton, Aleksandar Aleksov, Brandon C. Marin, Yonggang Li, Leonel Arana, Suddhasattwa Nad, Haobo Chen, Tarek Ibrahim
  • Publication number: 20210305668
    Abstract: A method of fabricating an RF filter on a semiconductor package comprises forming a first dielectric buildup film. A second dielectric buildup film is formed over the first dielectric buildup film, the second dielectric buildup film comprising a dielectric material that contains a metallization catalyst, wherein the dielectric material comprises one of an epoxy-polymer blend dielectric material, silicon dioxide and silicon nitride, and a low-k dielectric. A trench is formed in the second dielectric buildup film with laser ablation, wherein the laser ablation selectively activates sidewalls of the trench for electroless metal deposition. A metal selectively is plated to sidewalls of the trench based at least in part on the metallization catalyst and immersion in an electroless solution. A low-loss buildup film is formed over the metal that substantially fills the trench.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventors: Brandon C. MARIN, Jeremy D. ECTON, Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Yonggang LI, Dilan SENEVIRATNE
  • Patent number: 11081768
    Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Jeremy D. Ecton, Aleksandar Aleksov, Kristof Darmawikarta, Yonggang Li, Dilan Seneviratne
  • Publication number: 20210213694
    Abstract: The light guide film product processing apparatus provided in the present invention relates to the field of light guide film processing, and includes an unwinding device for transmitting a first light guide film, a dot processing device, a cooling device, a cutting device, a waste collecting device, and a product collecting device that are sequentially installed along the transmission direction of the first light guide film, and a linkage controller; the dot processing device transfers dots on both sides of the first light guide film, the cooling device cools the first light guide film after dot processing, the cutting device cuts the cooled first light guide film, the waste collecting device is configured to wind a second light guide film, and the second light guide film is a remaining material after the first light guide film is cut into a light guide film product; and the included angle formed between the winding and transmission direction of the second light guide film and the transmission direction of th
    Type: Application
    Filed: June 10, 2020
    Publication date: July 15, 2021
    Applicant: NANJING BREADY ELECTRONICS CO., LTD.
    Inventors: Yong LIU, Yonggang LI
  • Patent number: 10985080
    Abstract: An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Pramod Malatkar, Kyle Yazzie, Naga Sivakumar Yagnamurthy, Richard J. Harries, Dilan Seneviratne, Praneeth Akkinepally, Xuefei Wan, Yonggang Li, Robert L. Sankman
  • Patent number: 10910327
    Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Brandon C Marin, Vahidreza Parichehreh, Jeremy D Ecton
  • Publication number: 20200373261
    Abstract: A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Brandon C. MARIN, Jeremy D. ECTON, Aleksandar ALEKSOV, Kristof DARMAWIKARTA, Yonggang LI, Dilan SENEVIRATNE
  • Publication number: 20200312771
    Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 1, 2020
    Inventors: Bai NIE, Gang DUAN, Srinivas PIETAMBARAM, Jesse JONES, Yosuke KANAOKA, Hongxia FENG, Dingying XU, Rahul MANEPALLI, Sameer PAITAL, Kristof DARMAWIKARTA, Yonggang LI, Meizi JIAO, Chong ZHANG, Matthew TINGEY, Jung Kyu HAN, Haobo CHEN
  • Publication number: 20200312787
    Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Yonggang Li, Brandon C. Marin, Vahidreza Parichehreh, Jeremy D. Ecton
  • Publication number: 20200176272
    Abstract: Embodiments include methods for selective electroless plating of dielectric layers and devices formed by such processes. According to an embodiment, patterned surfaces are formed in a dielectric layer that includes metallic ceramic fillers. In some embodiments, the patterned surfaces form a line opening and a via opening that exposes a conductive pad. In an embodiment, the metallic ceramic fillers are activated to form activated surfaces over the patterned surfaces. A first metal is then deposited into the via opening with a first electroless solution that is a bottom-up deposition process. Thereafter, embodiments include forming a seed layer over exposed portions of the activated surfaces. In an embodiment, mid-gap states of the activated surfaces have an energy level approximately equal to a reduction potential of metal ions in a second electroless solution. Embodiments may then include depositing a second metal into the via opening with a third electroless solution.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 4, 2020
    Inventors: Vivek RAGHUNATHAN, Yonggang LI
  • Patent number: 10672701
    Abstract: Discussed generally herein are methods and devices for flexible fabrics or that otherwise include thin traces. A device can include a flexible polyimide material, and a first plurality of traces on the flexible polyimide material, wherein the first plurality of traces are patterned on the flexible polyimide material using laser spallation.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Vivek Raghunathan, Yonggang Li, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Publication number: 20200105685
    Abstract: Embodiments include one or more air core inductors (ACIs) and a method of forming the ACIs. The ACI includes a first inductor loop on a substrate. The first inductor loop has a first line and a second line. The first line has a first thickness that is greater than a second thickness of the second line. The ACI also includes a dielectric over the substrate and the first and second lines. The first line has a top surface above a top surface of the second line. The ACI further includes a second inductor loop on the dielectric and the first inductor loop. The second inductor loop has is coupled to the top surface of the first line of the first inductor loop. The first inductor loop may also have a third thickness, where the third thickness is the distance between the top surfaces of the first and second line.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Jeremy ECTON, Suddhasattwa NAD, Kristof DARMAWIKARTA, Yonggang LI, Xiaoying GUO
  • Publication number: 20200091053
    Abstract: Disclosed herein are integrated circuit (IC) package supports having inductors with magnetic material therein. For example, in some embodiments, an IC package support may include an inductor including a solenoid, a first portion of a magnetic material in an interior of the solenoid, and a second portion of magnetic material outside the interior of the solenoid.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Applicant: Intel Corporation
    Inventors: Sameer Paital, Srinivas V. Pietambaram, Yonggang Li, Kristof Kuwawi Darmawikarta, Gang Duan, Krishna Bharath, Michael James Hill
  • Publication number: 20200078884
    Abstract: A system and method of planarizing a layer are disclosed. Topography of the layer is measured to produce a topographic map, which is then digitized into blocks of that indicate different thickness variation. Laser conditions are assigned for each block, a laser steered to planarization blocks where material is to be removed, and the material ablated at each planarization block. In-situ monitoring of the surface profile provides feedback to adjust the laser conditions during planarization. When depth control is used, the laser is focused at a focal plane and has a focal depth beyond which no material is ablated and the laser is steered across the entire layer. A thin metal layer of higher ablation threshold than the dielectric layer formed over the layer provides added selectivity, with the laser conditions changed after ablation of the metal layer. Otherwise, planarization is limited to the planarization blocks.
    Type: Application
    Filed: September 7, 2018
    Publication date: March 12, 2020
    Inventors: Bai Nie, Yonggang Li
  • Publication number: 20200083164
    Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.
    Type: Application
    Filed: September 12, 2018
    Publication date: March 12, 2020
    Inventors: Brandon C. MARIN, Frank TRUONG, Shivasubramanian BALASUBRAMANIAN, Dilan SENEVIRATNE, Yonggang LI, Sameer PAITAL, Darko GRUJICIC, Rengarajan SHANMUGAM, Melissa WETTE, Srinivas PIETAMBARAM
  • Patent number: 10539294
    Abstract: A blind spot warning indication device for an exterior mirror of an automobile includes a light guide member. A plurality of wedge-shaped bosses are arranged side by side along an axis on the light guide member corresponding to a setting direction of the PCB. One side of each of the plurality of wedge-shaped bosses has a light incident end surface for aligning with a corresponding light source. An upper surface of each of the plurality of wedge-shaped bosses includes a light reflecting side having an optical pattern for reflecting and scattering. The reflecting side having the optical pattern is an upwardly convex arc surface. A lower surface of the wedge-shaped boss has a light emitting side. The outermost wedge-shaped boss has the largest curvature of the light-reflecting side compared to the other wedge-shaped bosses arranged side by side, and the outermost wedge-shaped boss has the longest length of the light-emitting side compared to the other wedge-shaped bosses arranged side by side.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 21, 2020
    Assignees: SMR Patents S.à.r.l., Ningbo SMR Huaxiang Automotive Mirrors Ltd.
    Inventors: Norbert Kürschner, Daniel Fritz, Yifei Feng, Yonggang Li, Weiping Lu
  • Publication number: 20200005990
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for embedding a magnetic core or a magnetic inductor in a substrate layer by applying a copper layer to a portion of the substrate layer, creating a structure in the substrate layer on top of at least part of the copper layer to identify a defined region within the substrate layer, and inserting a magnetic paste into the defined region where the copper layer identifies a side of the defined region and where the structure is to contain the magnetic paste within the defined region while the magnetic paste cures.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Sameer PAITAL, Srinivas PIETAMBARAM, Yonggang LI, Bai NIE, Kristof DARMAWIKARTA, Gang DUAN
  • Publication number: 20200005987
    Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Srinivas Pietambaram, Kristof Darmawikarta, Gang Duan, Yonggang Li, Sameer Paital
  • Publication number: 20190346111
    Abstract: A blind spot warning indication device for an exterior mirror of an automobile includes a light guide member. A plurality of wedge-shaped bosses are arranged side by side along an axis on the light guide member corresponding to a setting direction of the PCB. One side of each of the plurality of wedge-shaped bosses has a light incident end surface for aligning with a corresponding light source. An upper surface of each of the plurality of wedge-shaped bosses includes a light reflecting side having an optical pattern for reflecting and scattering. The reflecting side having the optical pattern is an upwardly convex arc surface. A lower surface of the wedge-shaped boss has a light emitting side. The outermost wedge-shaped boss has the largest curvature of the light-reflecting side compared to the other wedge-shaped bosses arranged side by side, and the outermost wedge-shaped boss has the longest length of the light-emitting side compared to the other wedge-shaped bosses arranged side by side.
    Type: Application
    Filed: July 25, 2019
    Publication date: November 14, 2019
    Applicants: SMR Patents S.à.r.l., Ningbo SMR Huaxiang Automotive Mirrors Ltd.
    Inventors: Norbert Kürschner, Daniel Fritz, Yifei Feng, Yonggang Li, Weiping Lu
  • Publication number: 20190319560
    Abstract: A motor driving circuit for driving a brushless motor with a sine wave driving mode in a continuous running phase is provided. The motor driving circuit includes a rotor position identifying module configured to identify a sector k in which a rotor of the brushless motor is currently located and an initial electrical angle ?k of the sector k, a speed calculation module configured to obtain an expected ?k of the rotor in the sector k by calculating the average speed of one or more sectors previous to the sector k; and a calculation/control module configured to determine a real-time electrical angle ?, determine a real-time equivalent voltage, and obtain a corresponding pulse modulation driving signal.
    Type: Application
    Filed: April 16, 2019
    Publication date: October 17, 2019
    Inventors: Jingxin SHI, Yonggang LI