Patents by Inventor Yongjun Jeff Hu

Yongjun Jeff Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011408
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Jordan D. Greenlee, Yongjun Jeff Hu
  • Patent number: 10998481
    Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
  • Patent number: 10991882
    Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher W. Petz, Yongjun Jeff Hu, Scott E. Sills, D. V. Nirmal Ramaswamy
  • Publication number: 20210111064
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process.
    Type: Application
    Filed: October 11, 2019
    Publication date: April 15, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Jordan D. Greenlee, Yongjun Jeff Hu
  • Patent number: 10971607
    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu
  • Patent number: 10923657
    Abstract: A memory cell comprising a threshold switching material over a first electrode on a substrate. The memory cell includes a second electrode over the threshold switching material and at least one dielectric material between the threshold switching material and at least one of the first electrode and the second electrode. A memory material overlies the second electrode. The dielectric material may directly contact the threshold switching material and each of the first electrode and the second electrode. Memory cells including only one dielectric material between the threshold switching material and an electrode are disclosed. A memory device including the memory cells and methods of forming the memory cells are also described.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Tsz W. Chan, Durai Vishak Nirmal Ramaswamy, Qian Tao, Yongjun Jeff Hu, Everett A. McTeer
  • Patent number: 10916564
    Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
  • Patent number: 10847367
    Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David R. Economy, Brian Beatty, John Mark Meldrim, Yongjun Jeff Hu, Jordan D. Greenlee
  • Publication number: 20200266210
    Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: Micron Technology, Inc.
    Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
  • Patent number: 10731273
    Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
  • Patent number: 10720574
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Tsz W. Chan, Yongjun Jeff Hu, Swapnil Lengade, Shu Qin, Everett Allen McTeer
  • Publication number: 20200211843
    Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: David Ross Economy, Brian Beatty, John Mark Meldrim, Yongjun Jeff Hu, Jordan D. Greenlee
  • Patent number: 10700091
    Abstract: Some embodiments include an assembly which has channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure has doped semiconductor material in direct contact with bottom regions of the channel material pillars. One or more of magnesium, scandium, yttrium and lanthanide elements is along the bottom regions of the channel material pillars. Some embodiments include methods of forming assemblies. A structure is formed, and a mass is formed against an upper surface of the structure. Plugs are formed within openings in the mass. The plugs comprise a second material over a first material. The first material includes one or more of magnesium, scandium, yttrium and lanthanide elements. Openings are formed to terminate on the first material, and are then extended through the first material. Channel material pillars are formed within the openings.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 30, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, John Mark Meldrim, Haoyu Li, Yongjun Jeff Hu, Christopher W. Petz, Daniel Billingsley, Everett A. McTeer
  • Patent number: 10692572
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 23, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Tsz W. Chan, Christopher W. Petz, Everett Allen McTeer
  • Publication number: 20200083238
    Abstract: Some embodiments include an integrated structure having semiconductor material within a region between two parallel surfaces. The semiconductor material has grain boundaries parallel to the parallel surfaces. At least one circuit component utilizes a region of the semiconductor material in a gated device. The semiconductor material has little if any metal therein so that the gated device has Ion/Ioff characteristics similar to if the semiconductor material had no metal therein. Some embodiments include a method in which semiconductor material is provided between a pair of parallel surfaces, and in which the parallel surfaces and semiconductor material extend between a first end and a second end. Metal is formed adjacent the first end, and gettering material is formed adjacent the second end. Thermal processing induces crystallization of the semiconductor material and drives the metal along the semiconductor material and into the gettering material. The gettering material is then removed.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Allen McTeer
  • Publication number: 20200035891
    Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Yongjun Jeff Hu, John Mark Meldrim, Shanming Mou, Everett Allen McTeer
  • Patent number: 10546848
    Abstract: An integrated assembly includes an insulative mass with a first region adjacent to a second region. The first region has a greater amount of one or more inert interstitial elements incorporated therein than does the second region. Some embodiments include an integrated assembly which has vertically-extending channel material pillars, and which has memory cells along the channel material pillars. A conductive structure is under the channel material pillars. The conductive structure includes doped semiconductor material in direct contact with bottom regions of the channel material pillars. An insulative mass is along the bottom regions of the channel material pillars. The insulative mass has an upper region over a lower region. The lower region has a greater amount of one or more inert interstitial elements incorporated therein than does the upper region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Everett A. McTeer, Christopher W. Petz, Haoyu Li, John Mark Meldrim, Yongjun Jeff Hu
  • Patent number: 10546895
    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such memory device includes a first electrode material formed on a word line material. A selector device material is formed on the first electrode material. A second electrode material is formed on the selector device material. A phase change material is formed on the second electrode material. A third electrode material is formed on the phase change material. An adhesion species is plasma doped into sidewalls of the memory stack and a liner material is formed on the sidewalls of the memory stack. The adhesion species intermixes with an element of the memory stack and the sidewall liner to terminate unsatisfied atomic bonds of the element and the sidewall liner.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yongjun Jeff Hu, Tsz W. Chan, Swapnil Lengade, Everett Allen McTeer, Shu Qin
  • Publication number: 20200013955
    Abstract: A resistive memory element comprises a first electrode, an active material over the first electrode, a buffer material over the active material and comprising longitudinally extending, columnar grains of crystalline material, an ion reservoir material over the buffer material, and a second electrode over the ion reservoir material. A memory cell, a memory device, an electronic system, and a method of forming a resistive memory element are also described.
    Type: Application
    Filed: August 27, 2019
    Publication date: January 9, 2020
    Inventors: Christopher W. Petz, Yongjun Jeff Hu, Scott E. Sills, D. V. Nirmal Ramaswamy
  • Patent number: 10529834
    Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Yongjun Jeff Hu