Patents by Inventor Yongping Ding
Yongping Ding has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220348512Abstract: The present disclosure discloses a modified calcium silicate board, and belongs to the technical field of floors and decorative boards. A modification method comprises steps of: dipping a calcium silicate board in a silicon dioxide solution with a solid content of 95% or more, completely absorbing the silicon dioxide solution until the calcium silicate board is saturated, and drying the dipped calcium silicate board; and carrying out sizing hardening on any surface of the modified calcium silicate board to obtain the calcium silicate board, so as to enable the triamine impregnated paper to be directly laminated with the calcium silicate board in a hot-pressing manner, and enable the surface bonding strength to reach 1 MPa; wood veneers, fireproof plates and other materials are subjected to coldbonding, the peeling strength of the product meets the requirements, and the practicability of the calcium silicate board is effectively improved.Type: ApplicationFiled: October 29, 2021Publication date: November 3, 2022Inventors: Haibing Gu, Yongping Ding
-
Publication number: 20200303517Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.Type: ApplicationFiled: May 22, 2020Publication date: September 24, 2020Inventors: Yongping Ding, Sik Lui, Madhur Bobde, Lei Zhang, Jongoh Kim, John Chen
-
Patent number: 10665711Abstract: A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.Type: GrantFiled: June 24, 2019Date of Patent: May 26, 2020Assignee: VISHAY SILICONIX, LLCInventors: Ayman Shibib, Kyle Terrill, Yongping Ding, Jinman Yang
-
Patent number: 10522666Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.Type: GrantFiled: March 9, 2018Date of Patent: December 31, 2019Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
-
Publication number: 20190312137Abstract: A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.Type: ApplicationFiled: June 24, 2019Publication date: October 10, 2019Inventors: Ayman SHIBIB, Kyle TERRILL, Yongping DING, Jinman YANG
-
Patent number: 10381473Abstract: A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.Type: GrantFiled: July 6, 2017Date of Patent: August 13, 2019Assignee: VISHAY-SILICONIXInventors: Ayman Shibib, Kyle Terrill, Yongping Ding, Jinman Yang
-
Patent number: 10115814Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.Type: GrantFiled: January 19, 2018Date of Patent: October 30, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yongping Ding, Lei Zhang, Hong Chang, Jongoh Kim, John Chen
-
Patent number: 10050134Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.Type: GrantFiled: June 8, 2016Date of Patent: August 14, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
-
Publication number: 20180204937Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.Type: ApplicationFiled: March 9, 2018Publication date: July 19, 2018Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
-
Patent number: 9997593Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.Type: GrantFiled: July 10, 2017Date of Patent: June 12, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.Inventors: Yongping Ding, Hamza Yilmaz, Xiaobin Wang, Madhur Bobde
-
Publication number: 20180158942Abstract: A high-electron-mobility transistor (HEMT) includes a substrate layer of silicon, a first contact disposed on a first surface of the substrate layer, and a number of layers disposed on a second surface of the substrate layer opposite the first surface. A second contact and a gate contact are disposed on those layers. A trench containing conducting material extends completely through the layers and into the substrate layer. In an embodiment of the HEMT, the first contact is a drain contact and the second contact is a source contact. In another embodiment of the HEMT, the first contact is a source contact and the second contact is a drain contact.Type: ApplicationFiled: July 6, 2017Publication date: June 7, 2018Inventors: Ayman SHIBIB, Kyle TERRILL, Yongping DING, Jinman YANG
-
Publication number: 20180145167Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.Type: ApplicationFiled: January 19, 2018Publication date: May 24, 2018Inventors: Yongping Ding, Lei Zhang, Hong Chang, Jongoh Kim, John Chen
-
Patent number: 9887283Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device comprises a plurality of trenches each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.Type: GrantFiled: May 10, 2013Date of Patent: February 6, 2018Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yongping Ding, Lei Zhang, Hong Chang, Jongoh Kim, John Chen
-
Patent number: 9865678Abstract: A semiconductor device includes a semiconductor substrate and epitaxial layer of a first conductivity type with the epitaxial layer on a top surface of the substrate. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the epitaxial layer. A first conductivity type source region is inside the body region and a drain is at a bottom surface of the substrate. An inslated gate overlaps the source and body regions. First and second trenches in the epitaxial layer are lined with insulation material and filled with electrically conductive material. Second conductivity type buried regions are positioned below the trenches. Second conductivity type charge linking paths along one or more walls of the first trench electrically connect a first buried region to the body region. A second buried region is separated from the body region by portions of the expitaxial layer.Type: GrantFiled: August 12, 2016Date of Patent: January 9, 2018Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATEDInventors: Anup Bhalla, Hamza Yilmaz, Madhur Bobde, Lingpeng Guan, Jun Hu, Jongoh Kim, Yongping Ding
-
Publication number: 20170373139Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.Type: ApplicationFiled: July 10, 2017Publication date: December 28, 2017Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.Inventors: Yongping Ding, Hamza Yilmaz, Xiaobin Wang, Madhur Bobde
-
Patent number: 9755052Abstract: A semiconductor power device disposed on a semiconductor substrate comprises a plurality of trenches formed at a top portion of the semiconductor substrate extending laterally across the semiconductor substrate along a longitudinal direction each having a nonlinear portion comprising a sidewall perpendicular to a longitudinal direction of the trench and extends vertically downward from a top surface to a trench bottom surface. The semiconductor power device further includes a trench bottom dopant region disposed below the trench bottom surface and a sidewall dopant region disposed along the perpendicular sidewall wherein the sidewall dopant region extends vertically downward along the perpendicular sidewall of the trench to reach the trench bottom dopant region and pick-up the trench bottom dopant region to the top surface of the semiconductor substrate.Type: GrantFiled: August 27, 2013Date of Patent: September 5, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yongping Ding, Sik Lui, Madhur Bobde, Lei Zhang, Jongoh Kim, John Chen
-
Patent number: 9704948Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole.Type: GrantFiled: August 9, 2014Date of Patent: July 11, 2017Assignee: Alpha & Omega Semiconductor (Cayman), Ltd.Inventors: Yongping Ding, Hamza Yilmaz, Xiaobin Wang, Madhur Bobde
-
Patent number: 9627526Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.Type: GrantFiled: March 24, 2014Date of Patent: April 18, 2017Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
-
Publication number: 20170069750Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.Type: ApplicationFiled: March 24, 2014Publication date: March 9, 2017Applicant: ALPHA & OMEGA SEMICONDUCTOR INCORPORATEDInventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
-
Publication number: 20160372542Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.Type: ApplicationFiled: July 12, 2014Publication date: December 22, 2016Inventors: Yeeheng Lee, Madhur Bobde, Yongping Ding, Jongoh Kim, Anup Bhalla