Patents by Inventor Yongseok Kim

Yongseok Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10991939
    Abstract: A negative active material for a rechargeable lithium battery includes a silicon-carbon composite including crystalline carbon and a silicon particle. The silicon-carbon composite further includes an alkali metal or an alkaline-earth metal. The alkali metal or the alkaline-earth metal is present in the silicon-carbon composite in an amount of greater than or equal to about 500 ppm and less than about 5,000 ppm by weight.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Yongseok Kim, Jaehou Nah, Yeonjoo Choi
  • Publication number: 20210118968
    Abstract: A display device includes a substrate having a top surface, a bottom surface, and a first contact hole passing through the top surface and the bottom surface; a thin film transistor disposed above the top surface and including a semiconductor layer; a display element connected to the thin film transistor; a top conductive pattern disposed between the substrate and the thin film transistor and overlapping the semiconductor layer of the thin film transistor; a bottom conductive pattern disposed on the bottom surface and connected to the top conductive pattern through the first contact hole; and a bottom planarization layer disposed on the bottom surface, the bottom planarization layer disposed on the bottom conductive pattern.
    Type: Application
    Filed: April 17, 2020
    Publication date: April 22, 2021
    Applicant: Samsung Display Co., Ltd.
    Inventors: Kangyoung LEE, Yongseok KIM, Dongchul SHIN, Hyunsup LEE, Gyehwan LIM
  • Patent number: 10979123
    Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokki Ahn, Kwangtaik Kim, Yongseok Kim, Chiwoo Lim
  • Patent number: 10978480
    Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghwan Lee, Yongseok Kim, Byoung-Taek Kim, Tae Hun Kim, Dongkyun Seo, Junhee Lim
  • Patent number: 10971238
    Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a plurality of word line blocks including a plurality of cell strings that are connected in parallel between a bit line and a common source line. Each of the cell strings includes a plurality of memory cell transistors that are stacked on a substrate in a vertical direction, a plurality of ground selection transistors that are connected in series between the plurality of memory cell transistors and the substrate, and a string selection transistor that is between the plurality of memory cell transistors and the bit line. In each of the cell strings, at least one of the plurality of ground selection transistors has a first threshold voltage, and remaining ones of the ground selection transistors have a second threshold voltage different from the first threshold voltage. Related methods of operating three-dimensional semiconductor memory devices are also provided.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 6, 2021
    Inventors: Kohji Kanamori, Yongseok Kim, Kyunghwan Lee, Junhee Lim
  • Publication number: 20210074798
    Abstract: A display apparatus includes: a substrate including a first surface, a second surface opposite the first surface, a display area defined on the first surface, and a non-display area defined on the second surface; a plurality of display elements at the display area on the first surface of the substrate; a driving circuit on the second surface and overlapping with the display area of the substrate; a first conductive pattern on the second surface of the substrate; and a second conductive pattern on the first surface of the substrate and connected to the first conductive pattern via a contact hole extending through the substrate. A surface roughness of the second surface of the substrate is greater than a surface roughness of the first surface of the substrate.
    Type: Application
    Filed: August 8, 2020
    Publication date: March 11, 2021
    Inventors: Yongseok KIM, Jaejoong KWON, Dongchul SHIN, Kangyoung LEE, Hyunsup LEE, Gyehwan LIM
  • Patent number: 10879967
    Abstract: Disclosed is a 5th generation (5G) or pre-5G communication system to be provided for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE). Examples of the present invention provide a beam selection and feedback device and method for minimizing complexity and overhead without performance deterioration in a beamforming MIMO wireless communication system. According to one example of the present invention, an apparatus of a receiving device in a wireless communication system comprises: a transceiver; and at least one processor, wherein the at least one processor is configured to: select at least one beam pair from among a plurality of transmission/reception beam pairs, and control the transceiver to transmit feedback information including indication information indicating whether the at least one beam pair is identical to a beam pair selected in a previous beamforming procedure.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung Ju Kim, Yongseok Kim, Hyunyong Lee
  • Publication number: 20200403079
    Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.
    Type: Application
    Filed: February 26, 2020
    Publication date: December 24, 2020
    Inventors: Jaeho HONG, Yongseok KIM, Hyuncheol KIM, Seokhan PARK, Satoru YAMADA, Kyunghwan LEE
  • Publication number: 20200395412
    Abstract: A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.
    Type: Application
    Filed: January 6, 2020
    Publication date: December 17, 2020
    Inventors: Kyunghwan LEE, Yongseok KIM, Taehun KIM, Seokhan PARK, Satoru YAMADA, Jaeho HONG
  • Publication number: 20200383546
    Abstract: Disclosed are a robot cleaner. The robot cleaner includes: a cleaner body configured to move in an area and clean the area; and a sensor assembly provided in the cleaner body. The sensor assembly includes: a main sensor configured to be moveable between a sensing position where the main sensor protrudes out of the cleaner body and a settled position where the main sensor is inside the cleaner body; a sensor position changer configured to allow the main sensor to move between the sensing position and the settled position; and a stopper configured to restrict the sensor position changer from allowing the main sensor at the sensing position to move towards the settled position.
    Type: Application
    Filed: June 3, 2020
    Publication date: December 10, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sinae KIM, Yongseok KIM, Minro YUN, Yeonkyu JEONG, Shin KIM, Jaeyoul JEONG
  • Publication number: 20200388632
    Abstract: A vertical memory device includes gate electrodes on a substrate. The gate electrodes are spaced apart from each other in a vertical direction. A channel penetrates the gate electrodes and extends in the vertical direction. A tunnel insulation pattern is formed on an outer sidewall of the channel. A charge trapping pattern structure is formed on an outer sidewall of the tunnel insulation pattern adjacent the gate electrodes in a horizontal direction. The charge trapping pattern structure includes upper and lower charge trapping patterns. A blocking pattern is formed between the charge trapping pattern structure and each of the adjacent gate electrodes. An upper surface of the upper charge trapping pattern is higher than an upper surface of the adjacent gate electrode. A lower surface of the lower charge trapping pattern is lower than a lower surface of an adjacent gate electrode.
    Type: Application
    Filed: January 27, 2020
    Publication date: December 10, 2020
    Inventors: KYUNGHWAN LEE, Kwangsoo Kim, Taehun Kim, Yongseok Kim, Kohji Kanamori
  • Publication number: 20200381448
    Abstract: Three-dimensional semiconductor memory devices are provided. A three-dimensional semiconductor memory device includes a stack structure that includes gate electrodes on a substrate. The three-dimensional semiconductor memory device includes a first vertical structure, a second vertical structure, a third vertical structure, and a fourth vertical structure that penetrate the stack structure and are sequentially arranged in a zigzag shape along a first direction. Moreover, the three-dimensional semiconductor memory device includes a first bit line that extends in the first direction. The first bit line vertically overlaps the second vertical structure and the fourth vertical structure. Centers of the second and fourth vertical structures are spaced apart at the same distance from the first bit line. The first vertical structure is spaced apart at a first distance from the first bit line. The third vertical structure is spaced apart at a second distance from the first bit line.
    Type: Application
    Filed: December 11, 2019
    Publication date: December 3, 2020
    Inventors: Kyunghwan Lee, Yongseok Kim, Kohji Kanamori, Minhan Shin
  • Publication number: 20200365560
    Abstract: A semiconductor device includes a first semiconductor structure comprising a substrate and a circuit element, and a second semiconductor structure connected to the first semiconductor structure. The second semiconductor structure includes a base layer, a first memory cell structure, a second memory cell structure, and common bit lines between the first memory cell structure and the second memory cell structure. The first memory cell structure includes first gate electrodes, first channel structures, and first string select channel structures. The second memory cell structure includes second gate electrodes, second channel structures, second string select channel structures, and connection regions between the second channel structures and the second string select channel structures.
    Type: Application
    Filed: January 6, 2020
    Publication date: November 19, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kohji KANAMORI, Yongseok KIM, Kyunghwan LEE, Junhee LIM, Jeehoon HAN
  • Publication number: 20200343307
    Abstract: A semiconductor memory device includes a stack structure comprising a plurality of insulating layers and a plurality of interconnection layers that are alternately and repeatedly stacked. A pillar structure is disposed on a side surface of the stack structure. The pillar structure includes an insulating pillar and a variable resistance layer disposed on the insulating pillar and positioned between insulating pillar and the stack structure. A channel layer is disposed on the variable resistance layer and is positioned between the variable resistance layer and the stack structure. A gate dielectric layer is disposed on the channel layer and is positioned between the plurality of interconnection layers and the channel layer. The channel layer is disposed between the variable resistance layer and the gate dielectric layer.
    Type: Application
    Filed: October 18, 2019
    Publication date: October 29, 2020
    Inventors: Kyunghwan Lee, Yongseok Kim, Kohji Kanamori
  • Patent number: D900763
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: November 3, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Sangik Lee, Hyojin Won, Yongseok Kim, Yooseok Kim
  • Patent number: D900766
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: November 3, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: Yooseok Kim, Hyojin Won, Yongseok Kim, Sangik Lee
  • Patent number: D911299
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: February 23, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Yongseok Kim, Yuonui Chong, Misun Park, Yooseok Kim, Minji Seo
  • Patent number: D911993
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: March 2, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Yooseok Kim, Yongseok Kim, Yuonui Chong, Misun Park, Minji Seo
  • Patent number: D914627
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 30, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Yongseok Kim, Yuonui Chong, Misun Park, Yooseok Kim, Minji Seo
  • Patent number: D915317
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: April 6, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Yongseok Kim, Yuonui Chong, Yooseok Kim, Misun Park, Minji Seo