Abstract: Disclosed is a CMOS power amplifier. A temperature compensation circuit of a CMOS power amplifier may include: a bias circuit unit supplying a gate bias voltage to a power amplification circuit part; a bias detection unit determining a class type of the power amplification circuit part according to the gate bias voltage; a temperature detection unit detecting a temperature-proportional voltage in proportion to ambient temperature; a temperature compensation control unit generating a compensation control value according to the temperature-proportion voltage in the class type determined by the bias detection unit; and a conversion unit converting the compensation control value of the temperature compensation control unit into a linear bias control value and providing the linear bias control value to the bias circuit unit, wherein the bias circuit unit compensates the gate bias voltage according to the linear bias control value of the conversion unit.

Abstract: There is provided a power amplifier that can maintain a constant gain by detecting a level of a signal being input and a level of a signal being output. A power amplifier according to an aspect of the invention may include: an amplification section having at least one amplification unit amplifying an input signal according to an adjustable gain to thereby output the amplified input signal; a detection section detecting signal levels of an input signal and an output signal of the amplification section; and a gain maintaining section controlling a bias power according to a detection result of the detection section so that a gain of the amplification section is maintained within a predetermined gain range.

Abstract: There is provided a power amplifier with a variable supply of bias power according to a look-up table having a voltage value determined based on a level of an RF signal being input to the power amplifier to thereby increase power efficiency. A power amplifier according to an aspect of the invention may include an amplification section amplifying an input signal according to a bias voltage being supplied; and a bias supply section comparing a level of the input signal with a look-up table set in advance and supplying a bias voltage to the amplification section according to a result of the comparison.

Abstract: Disclosed is a CMOS power amplifier. A temperature compensation circuit of a CMOS power amplifier may include: a bias circuit unit supplying a gate bias voltage to a power amplification circuit part; a bias detection unit determining a class type of the power amplification circuit part according to the gate bias voltage; a temperature detection unit detecting a temperature-proportional voltage in proportion to ambient temperature; a temperature compensation control unit generating a compensation control value according to the temperature-proportion voltage in the class type determined by the bias detection unit; and a conversion unit converting the compensation control value of the temperature compensation control unit into a linear bias control value and providing the linear bias control value to the bias circuit unit, wherein the bias circuit unit compensates the gate bias voltage according to the linear bias control value of the conversion unit.

Abstract: A buffer amplifier has high input impedance and is less affected by temperature by supplying independent bias power to each of amplification units. The buffer amplifier includes a bias supply unit supplying bias power having a preset voltage level, an amplification unit receiving preset driving power and the bias power from the bias supply unit to amplify an input signal, and a compensation unit compensating for current unbalance of the driving power supplied to the amplification unit.

Abstract: The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof.

Abstract: There is provided a power amplifier that can maintain a constant gain by detecting a level of a signal being input and a level of a signal being output. A power amplifier according to an aspect of the invention may include: an amplification section having at least one amplification unit amplifying an input signal according to an adjustable gain to thereby output the amplified input signal; a detection section detecting signal levels of an input signal and an output signal of the amplification section; and a gain maintaining section controlling a bias power according to a detection result of the detection section so that a gain of the amplification section is maintained within a predetermined gain range.

Abstract: There is provided a power amplifier with a variable supply of bias power according to a look-up table having a voltage value determined based on a level of an RF signal being input to the power amplifier to thereby increase power efficiency. A power amplifier according to an aspect of the invention may include an amplification section amplifying an input signal according to a bias voltage being supplied; and a bias supply section comparing a level of the input signal with a look-up table set in advance and supplying a bias voltage to the amplification section according to a result of the comparison.

Abstract: The present invention relates to and auto frequency calibrator, a method thereof, and a frequency synthesizer using it. The auto frequency calibrator includes a capacitor bank selector that is operated as an open loop and compares a frequency signal having integer-divided reference frequency with the reference frequency signal to select a capacitor bank corresponding to an output frequency; and a capacitor bank controller that is operated as a closed loop when the capacitor bank is selected and compares the output voltage corresponding to the output frequency with a preset voltage range to control the capacitor bank selected in the capacitor bank selector.

Abstract: The present relates to a fractional-N frequency synthesizer improving noise characteristics and a method thereof.

Abstract: A buffer amplifier has high input impedance and is less affected by temperature by supplying independent bias power to each of amplification units. The buffer amplifier includes a bias supply unit supplying bias power having a preset voltage level, an amplification unit receiving preset driving power and the bias power from the bias supply unit to amplify an input signal, and a compensation unit compensating for current unbalance of the driving power supplied to the amplification unit.

Abstract: An integrated tracking filter includes: an amplifying unit having first to third terminals, the first terminal being connected to an input stage and the second terminal being connected to an output stage, and amplifying a signal from the input stage; a loading unit connected between a power source stage and the second terminal of the amplifying unit; a current source connected between the third terminal of the amplifying unit and a ground; and a switched LC filter unit connected between the third terminal of the amplifying unit and the ground and varying a pass band of the signal.

Abstract: A mixer includes, an input current generation unit generating an input current; a first path circuit unit including n number of transistors having sources connected in common to an output node of the input current generation unit; and a second path circuit unit including n number of transistors having sources connected in common to the output node of the input current generation unit, and respectively corresponding to the n number of transistors included in the first path circuit unit. Local oscillator signals sequentially phase-shifted by 180°/n are individually input to gates of the n number of transistors included in the first path circuit unit, and local oscillator signals having opposite phases to the local oscillator signals input to the gates of the corresponding transistors included in the first path circuit unit are individually input to gates of the n number of transistors included in the second path circuit unit.

Abstract: A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.

Abstract: The invention relates to method of determining a fractional division ratio using a sigma-delta modulator. In this method, the fractional division ratio of the sigma-delta modulator is set as k/q, where k is an integer input value of the sigma-delta modulator, and q is a value preset to determine a predetermined frequency resolution. A spur generated from the voltage controller oscillator according to the variation of k is measured while the value k is varied. When the spur takes place at a certain value of k where a frequency is lower than a predetermined reference frequency, the fractional division ratio is reset as k/(q+1) or k/(q?1) for the certain value of k. The reset fractional division ratio is provided to the divider.

Abstract: The invention provides a low divide ratio programmable frequency divider of a fractional-N type applied to a digital MOPLL tuner and a method thereof. In the invention, a divide ratio assigner assigns divide data as a main divide ratio and a pulse swallow value according to a first or a second dividing operation mode in response to a mode selection signal. A prescaler operates on the first or second divide operation mode in response to the mode selection signal. Also, a main counter divides a frequency from the prescaler by the main divide ratio. Further, a pulse swallow counter counts a clock of the main counter while outputting a pulse swallow signal to the prescaler. The pulse swallow signal has a swallow level if a counting value corresponds to the pulse swallow value, and a non-swallow level if the counting value does not correspond to the pulse swallow value.

Abstract: A phase frequency detector for improving in-band phase noise characteristics of a PLL is disclosed. The phase frequency detector compares a reference frequency with a division frequency created by dividing an output frequency of a voltage controlled oscillator (VCO) by a predetermined division ratio, creates a phase-difference signal corresponding to a phase difference between the reference frequency and the division frequency, and improves noise characteristics.