Patents by Inventor Yoon-Jae Shin
Yoon-Jae Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136067Abstract: A method for monitoring an object is provided. The method includes the steps of: in response to information on a behavior of a domestic animal being estimated from sensor data measured by a sensor for the domestic animal using a machine learning-based behavior recognition model, estimating health status of the domestic animal with reference to the information on the behavior of the domestic animal and a health criterion for the domestic animal; and determining first breeding information on the domestic animal to be provided to a user on the basis of the health status.Type: ApplicationFiled: August 22, 2021Publication date: April 25, 2024Applicant: Bodit Inc.Inventors: Kwang Jae Choo, Min Yong Shin, Heung Jong Yoo, Yoon Chul Choi, Seongjin Kim, Nayeon Kim
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Patent number: 11962001Abstract: Disclosed is a positive electrode material for a lithium secondary battery. The positive electrode material includes a positive electrode active material formed of Li—[Mn—Ti]-M-O-based material including a transition metal (M) to enable reversible intercalation and deintercalation of lithium and molybdenum oxide. The positive electrode active material is coated with the molybdenum oxide to form a coating layer on a surface thereof.Type: GrantFiled: October 6, 2021Date of Patent: April 16, 2024Assignees: Hyundai Motor Company, Kia Corporation, Industry Academy Cooperation Foundation of Sejong UniversityInventors: Seung Min Oh, Jun Ki Rhee, Yoon Sung Lee, Ji Eun Lee, Sung Ho Ban, Ko Eun Kim, Woo Young Jin, Sang Mok Park, Sang Hun Lee, Seung Taek Myung, Hee Jae Kim, Min Young Shin
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Patent number: 11937476Abstract: A display device comprises a substrate; a circuit array layer comprising pixel drivers, data lines, first dummy lines, and second dummy lines; and a light emitting array layer. The display area comprises middle, first side, and second side regions. The data lines comprise first, second, and third data lines disposed in the middle, first side, and second side regions, respectively. The first dummy lines comprise a first data detour line disposed in the first side region and adjacent to a part of the second data line, and auxiliary lines. The second dummy lines comprise a second data detour line configured to connect the first data detour line to the third data line, and additional lines. The auxiliary lines comprise a bias auxiliary line to which a bias power is applied; and a second power auxiliary line to which a second power is applied.Type: GrantFiled: May 4, 2023Date of Patent: March 19, 2024Assignee: Samsung Display Co., Ltd.Inventors: Jin Sung An, Sung Ho Kim, Yong Jae Kim, Yun Hwan Park, Yoon Jee Shin, Sug Woo Jung, Hyun Wook Choi
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Patent number: 10546635Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.Type: GrantFiled: March 4, 2019Date of Patent: January 28, 2020Assignee: SK hynix Inc.Inventors: Jung Hyuk Yoon, Yoon Jae Shin
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Patent number: 10516384Abstract: A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.Type: GrantFiled: October 15, 2018Date of Patent: December 24, 2019Assignee: SK hynix Inc.Inventors: Yoon Jae Shin, Jae Boum Park
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Publication number: 20190305760Abstract: A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.Type: ApplicationFiled: October 15, 2018Publication date: October 3, 2019Applicant: SK hynix Inc.Inventors: Yoon Jae SHIN, Jae Boum PARK
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Publication number: 20190198102Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.Type: ApplicationFiled: March 4, 2019Publication date: June 27, 2019Applicant: SK hynix Inc.Inventors: Jung Hyuk YOON, Yoon Jae SHIN
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Patent number: 10249367Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.Type: GrantFiled: May 1, 2017Date of Patent: April 2, 2019Assignee: SK hynix Inc.Inventors: Jung Hyuk Yoon, Yoon Jae Shin
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Patent number: 10210927Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.Type: GrantFiled: May 1, 2017Date of Patent: February 19, 2019Assignee: SK hynix Inc.Inventors: Jung Hyuk Yoon, Yoon Jae Shin
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Publication number: 20170236582Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Applicant: SK hynix Inc.Inventors: Jung Hyuk YOON, Yoon Jae SHIN
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Publication number: 20170236583Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.Type: ApplicationFiled: May 1, 2017Publication date: August 17, 2017Applicant: SK hynix Inc.Inventors: Jung Hyuk YOON, Yoon Jae SHIN
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Patent number: 9690310Abstract: An internal voltage generator includes: a comparison block suitable for comparing an internal voltage with a reference voltage and generating a first comparison signal having an analog level corresponding to a comparison result a first driving block suitable for driving an output terminal of the internal voltage with a source voltage in response to the first comparison signal; a logic block suitable for generating a second comparison signal having a logic level based on the first comparison signal; and a second driving block suitable for driving the output terminal of the internal voltage with the source voltage based on the second comparison signal.Type: GrantFiled: January 15, 2016Date of Patent: June 27, 2017Assignee: SK Hynix Inc.Inventor: Yoon-Jae Shin
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Patent number: 9659640Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.Type: GrantFiled: November 15, 2013Date of Patent: May 23, 2017Assignee: SK hynix Inc.Inventors: Jung Hyuk Yoon, Yoon Jae Shin
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Publication number: 20170099045Abstract: A semiconductor device includes: an initialization block suitable for initializing an internal voltage terminal based on a first voltage of a first voltage terminal; a feedback block suitable for generating a feedback voltage based on an internal voltage of the internal voltage terminal; a comparison block suitable for comparing the feedback voltage with a reference voltage to generate a comparison signal; a driving block suitable for driving the internal voltage terminal with a second voltage of a second voltage terminal in response to the comparison signal; and a leakage current prevention block suitable for selectively blocking a current path passing through the internal voltage terminal, the driving block and the second voltage terminal in response to a power-up signal corresponding to the first voltage.Type: ApplicationFiled: March 9, 2016Publication date: April 6, 2017Inventors: Yoon-Jae SHIN, Kyeong-Tae KIM
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Publication number: 20170045900Abstract: An internal voltage generator includes: a comparison block suitable for comparing an internal voltage with a reference voltage and generating a first comparison signal having an analog level corresponding to a comparison result a first driving block suitable for driving an output terminal of the internal voltage with a source voltage in response to the first comparison signal; a logic block suitable for generating a second comparison signal having a logic level based on the first comparison signal; and a second driving block suitable for driving the output terminal of the internal voltage with the source voltage based on the second comparison signal.Type: ApplicationFiled: January 15, 2016Publication date: February 16, 2017Inventor: Yoon-Jae SHIN
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Patent number: 9542124Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.Type: GrantFiled: March 19, 2014Date of Patent: January 10, 2017Assignee: SK hynix Inc.Inventors: Byoung-Chan Oh, Yoon-Jae Shin
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Patent number: 9508398Abstract: A semiconductor memory device includes a voltage generation unit suitable for selecting one of the voltages which are supplied to a first and a second source voltage terminals, as a source voltage based on a driving mode signal, and generating a bit line precharge voltage by dividing the source voltage according to a resistance ratio determined based on the driving mode signal; a sense amplifier driving unit suitable for receiving the bit line precharge voltage based on a bit line precharge signal and a sense amplifier control signal, and providing a driving voltage through a pull-up power line and a pull-down power line; and a bit line sense amplifier suitable for sensing and amplifying data of a bit line pair by using the driving voltage supplied through the pull-up power line and the pull-down power line.Type: GrantFiled: February 18, 2016Date of Patent: November 29, 2016Assignee: SK Hynix Inc.Inventors: Yoon-Jae Shin, Jae-Boum Park
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Patent number: 9508411Abstract: A word line driver circuit according to an embodiment includes a driving unit configured to output a sub word line driving signal in response to a word line select signal and a main word line driving signal, a transmission unit configured to transmit the sub word line driving signal to a word line in response to a first enable signal, and a precharge unit configured to precharge a potential of the word line.Type: GrantFiled: September 15, 2014Date of Patent: November 29, 2016Assignee: SK HYNIX INC.Inventors: Chang Yong Ahn, Yoon Jae Shin
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Patent number: 9437289Abstract: Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.Type: GrantFiled: March 19, 2014Date of Patent: September 6, 2016Assignee: SK hynix Inc.Inventors: Byoung-Chan Oh, Yoon-Jae Shin
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Patent number: 9368236Abstract: A semiconductor memory apparatus may include a read/write circuit unit configured to receive an external voltage, to read data from a memory cell array, and to generate a pre-read signal, while an internal voltage is generated during a test mode, and a controller configured to selectively drive a write circuit unit in response to the pre-read signal.Type: GrantFiled: September 8, 2014Date of Patent: June 14, 2016Assignee: SK hynix Inc.Inventors: Chang Yong Ahn, Yoon Jae Shin