Patents by Inventor Yoon-Jae Shin

Yoon-Jae Shin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152686
    Abstract: An electronic device which includes a housing is provided. The housing includes a first surface, a second surface facing away from the first surface, and a side member surrounding a space between the first surface and the second surface, a display that is exposed through a substantial portion of the first surface of the housing, a first radiator that forms a portion of the side member, a PCB that is positioned within the housing and includes a ground layer, a communication circuit that is positioned on the PCB, and a conductive pattern having a length corresponding to a length of the first radiator.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 19, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Ryul Shin, Him Chan YuN, Yoon Jae Lee, Jung Hoon Seo, Ui Chul Jeong
  • Patent number: 10546635
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: January 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Patent number: 10516384
    Abstract: A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 24, 2019
    Assignee: SK hynix Inc.
    Inventors: Yoon Jae Shin, Jae Boum Park
  • Publication number: 20190305760
    Abstract: A voltage generation circuit is provided. The voltage generation circuit may include an enable signal generator, a voltage controller, and a voltage driver. The enable signal generator may generate an enable signal based on a test signal and an active signal. During activation of the enable signal, the voltage controller may compare a reference voltage with a feedback voltage, amplify the result of comparison, and generate a drive voltage. The voltage driver may output an internal voltage by driving the drive voltage, and generate the feedback voltage corresponding to the internal voltage. The feedback voltage may be pulled down during activation of the enable signal.
    Type: Application
    Filed: October 15, 2018
    Publication date: October 3, 2019
    Applicant: SK hynix Inc.
    Inventors: Yoon Jae SHIN, Jae Boum PARK
  • Publication number: 20190198102
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Applicant: SK hynix Inc.
    Inventors: Jung Hyuk YOON, Yoon Jae SHIN
  • Patent number: 10249367
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 2, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Patent number: 10210927
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 19, 2019
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Publication number: 20170236582
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Applicant: SK hynix Inc.
    Inventors: Jung Hyuk YOON, Yoon Jae SHIN
  • Publication number: 20170236583
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Applicant: SK hynix Inc.
    Inventors: Jung Hyuk YOON, Yoon Jae SHIN
  • Patent number: 9690310
    Abstract: An internal voltage generator includes: a comparison block suitable for comparing an internal voltage with a reference voltage and generating a first comparison signal having an analog level corresponding to a comparison result a first driving block suitable for driving an output terminal of the internal voltage with a source voltage in response to the first comparison signal; a logic block suitable for generating a second comparison signal having a logic level based on the first comparison signal; and a second driving block suitable for driving the output terminal of the internal voltage with the source voltage based on the second comparison signal.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: June 27, 2017
    Assignee: SK Hynix Inc.
    Inventor: Yoon-Jae Shin
  • Patent number: 9659640
    Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: May 23, 2017
    Assignee: SK hynix Inc.
    Inventors: Jung Hyuk Yoon, Yoon Jae Shin
  • Publication number: 20170099045
    Abstract: A semiconductor device includes: an initialization block suitable for initializing an internal voltage terminal based on a first voltage of a first voltage terminal; a feedback block suitable for generating a feedback voltage based on an internal voltage of the internal voltage terminal; a comparison block suitable for comparing the feedback voltage with a reference voltage to generate a comparison signal; a driving block suitable for driving the internal voltage terminal with a second voltage of a second voltage terminal in response to the comparison signal; and a leakage current prevention block suitable for selectively blocking a current path passing through the internal voltage terminal, the driving block and the second voltage terminal in response to a power-up signal corresponding to the first voltage.
    Type: Application
    Filed: March 9, 2016
    Publication date: April 6, 2017
    Inventors: Yoon-Jae SHIN, Kyeong-Tae KIM
  • Publication number: 20170045900
    Abstract: An internal voltage generator includes: a comparison block suitable for comparing an internal voltage with a reference voltage and generating a first comparison signal having an analog level corresponding to a comparison result a first driving block suitable for driving an output terminal of the internal voltage with a source voltage in response to the first comparison signal; a logic block suitable for generating a second comparison signal having a logic level based on the first comparison signal; and a second driving block suitable for driving the output terminal of the internal voltage with the source voltage based on the second comparison signal.
    Type: Application
    Filed: January 15, 2016
    Publication date: February 16, 2017
    Inventor: Yoon-Jae SHIN
  • Patent number: 9542124
    Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: January 10, 2017
    Assignee: SK hynix Inc.
    Inventors: Byoung-Chan Oh, Yoon-Jae Shin
  • Patent number: 9508398
    Abstract: A semiconductor memory device includes a voltage generation unit suitable for selecting one of the voltages which are supplied to a first and a second source voltage terminals, as a source voltage based on a driving mode signal, and generating a bit line precharge voltage by dividing the source voltage according to a resistance ratio determined based on the driving mode signal; a sense amplifier driving unit suitable for receiving the bit line precharge voltage based on a bit line precharge signal and a sense amplifier control signal, and providing a driving voltage through a pull-up power line and a pull-down power line; and a bit line sense amplifier suitable for sensing and amplifying data of a bit line pair by using the driving voltage supplied through the pull-up power line and the pull-down power line.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: November 29, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yoon-Jae Shin, Jae-Boum Park
  • Patent number: 9508411
    Abstract: A word line driver circuit according to an embodiment includes a driving unit configured to output a sub word line driving signal in response to a word line select signal and a main word line driving signal, a transmission unit configured to transmit the sub word line driving signal to a word line in response to a first enable signal, and a precharge unit configured to precharge a potential of the word line.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: November 29, 2016
    Assignee: SK HYNIX INC.
    Inventors: Chang Yong Ahn, Yoon Jae Shin
  • Patent number: 9437289
    Abstract: Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: September 6, 2016
    Assignee: SK hynix Inc.
    Inventors: Byoung-Chan Oh, Yoon-Jae Shin
  • Patent number: 9368236
    Abstract: A semiconductor memory apparatus may include a read/write circuit unit configured to receive an external voltage, to read data from a memory cell array, and to generate a pre-read signal, while an internal voltage is generated during a test mode, and a controller configured to selectively drive a write circuit unit in response to the pre-read signal.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: June 14, 2016
    Assignee: SK hynix Inc.
    Inventors: Chang Yong Ahn, Yoon Jae Shin
  • Patent number: 9355720
    Abstract: A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: May 31, 2016
    Assignee: SK HYNIX INC.
    Inventors: Chang Yong Ahn, Yoon Jae Shin, In Soo Lee, Jun Ho Cheon
  • Patent number: 9263125
    Abstract: A nonvolatile memory apparatus includes a memory cell array including a plurality of sub arrays. A plurality of analog-to-digital converters (ADCs) configured to sense sensing voltages outputted from memory cells of the plurality of sub arrays and a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of ADCs in one-to-one correspondence in a first operation mode, and electrically couple the plurality of ADCs with a terminal of a power supply voltage in a second operation mode.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventors: Min Chul Shin, Yoon Jae Shin