Patents by Inventor Yorito Sakano

Yorito Sakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11322534
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic apparatus which allow reduction of optical crosstalk. In an example of FIG. 5B, a charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. In an example of FIG. 5C, a charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a half (one side) of a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. The present disclosure can be applied to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 3, 2022
    Assignee: SONY CORPORATION
    Inventors: Masaaki Takizawa, Yasushi Tateshita, Takahiro Toyoshima, Takuya Toyofuku, Yorito Sakano, Motonobu Torii
  • Publication number: 20220093655
    Abstract: The present technology relates to a solid-state image sensing device and an electronic device for reducing noises. The solid-state image sensing device includes: a photoelectric conversion unit; a charge holding unit for holding charges transferred from the photoelectric conversion unit; a first transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit; and a light blocking part including a first light blocking part and a second light blocking part, in which the first light blocking part is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit, and covers the second surface, and is formed with a first opening, and the second light blocking part surrounds the side surface of the photoelectric conversion unit. The present technology is applicable to solid-state image sensing devices of backside irradiation type, for example.
    Type: Application
    Filed: December 3, 2021
    Publication date: March 24, 2022
    Inventors: HIROSHI TAYANAKA, KENTARO AKIYAMA, YORITO SAKANO, TAKASHI OINOUE, YOSHIYA HAGIMOTO, YUSUKE MATSUMURA, NAOYUKI SATO, YUKI MIYANAMI, YOICHI UEDA, RYOSUKE MATSUMOTO
  • Publication number: 20220038648
    Abstract: Degradation of image quality is suppressed. A solid-state imaging device according to an embodiment includes: a plurality of first photoelectric conversion elements having a first sensitivity; a plurality of second photoelectric conversion elements having a second sensitivity lower than the first sensitivity; a plurality of charge storage regions that stores charge generated by each of the plurality of second photoelectric conversion elements; a plurality of first color filters; and a plurality of second color filters. In each of the plurality of first photoelectric conversion elements, the second color filter for the second photoelectric conversion element included in the charge storage region closest to the first photoelectric conversion element transmit a wavelength component identical to that of the first color filter for the first photoelectric conversion element closest to the charge storage region.
    Type: Application
    Filed: November 14, 2019
    Publication date: February 3, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoko IIDA, Atsushi SUZUKI, Yorito SAKANO
  • Publication number: 20220037388
    Abstract: A wide dynamic range with single exposure is achieved. A solid-state imaging device according to an embodiment includes a first substrate including a photoelectric conversion element , and a second substrate including a capacitor positioned on a side opposite to a surface of incidence of light to the photoelectric conversion element in the first substrate, and configured to accumulate a charge transferred from the photoelectric conversion element.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 3, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masaaki TAKIZAWA, Yorito SAKANO
  • Publication number: 20220013557
    Abstract: There is provided a solid-state imaging device having a configuration suitable for high integration. The solid-state imaging device includes a semiconductor layer, a photoelectric converter, a storage capacitor, and a first transistor. The photoelectric converter is provided in the semiconductor layer, and generates an electric charge corresponding to a received light amount by photoelectric conversion. The storage capacitor is provided on the semiconductor layer, and includes a first insulating film having a first electrical film thickness. The first transistor is provided on the semiconductor layer, and includes a second insulating film having a second electrical film thickness larger than the first electrical film thickness.
    Type: Application
    Filed: November 19, 2019
    Publication date: January 13, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shogo FURUYA, Yorito SAKANO, Ryo TAKAHASHI, Atsushi SUZUKI, Ryoichi YOSHIKAWA, Jun SUENAGA, Shinichi KOGA, Yohei CHIBA, Tadamasa SHIOYAMA
  • Patent number: 11217612
    Abstract: The solid-state image sensing device includes a photoelectric conversion unit, a charge holding unit for holding charges transferred from the photoelectric conversion unit, a first transfer transistor for transferring charges from the photoelectric conversion unit to the charge holding unit, and a light blocking part including a first light blocking part and a second light blocking part, in which the first light blocking part is arranged between a second surface opposite to a first surface as a light receiving surface of the photoelectric conversion unit and the charge holding unit, and covers the second surface, and is formed with a first opening, and the second light blocking part surrounds the side surface of the photoelectric conversion unit.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: January 4, 2022
    Assignee: SONY CORPORATION
    Inventors: Hiroshi Tayanaka, Kentaro Akiyama, Yorito Sakano, Takashi Oinoue, Yoshiya Hagimoto, Yusuke Matsumura, Naoyuki Sato, Yuki Miyanami, Yoichi Ueda, Ryosuke Matsumoto
  • Patent number: 11122230
    Abstract: An imaging apparatus of the present disclosure includes: a first switch that couples a first light-receiving device and a first charge accumulation section to each other; a second switch that couples a predetermined node and the first charge accumulation section to each other; a third switch that applies a predetermined voltage to the predetermined node; a fourth switch that couples a second light-receiving device and a second charge accumulation section to each other; a fifth switch that couples the second charge accumulation section and the predetermined node to each other; an output section that outputs a pixel voltage; a driving section; and a processor that determines first to fourth values.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 14, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Ryosuke Nakamura, Yorito Sakano, Atsushi Suzuki
  • Patent number: 11082649
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic device capable of effectively preventing blooming. Provided is a solid-state imaging device including: a pixel array portion in which a plurality of pixels is two-dimensionally arranged, in which the pixels each include an in-pixel capacitance and a counter electrode of the in-pixel capacitance, the in-pixel capacitance being provided on a side opposite to a light incident surface of a photoelectric conversion element provided in a semiconductor substrate, the counter electrode being provided in the semiconductor substrate. The present disclosure can be applied to, for example, a back-illuminated CMOS image sensor.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 3, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Masaaki Takizawa, Yorito Sakano
  • Patent number: 11075237
    Abstract: There is provided a solid-state image sensor including pixels each at least including light receiving parts receiving light to generate charge, a transfer part transferring the charge accumulated in the light receiving parts, and memory parts holding the charge transferred via the transfer part, and a predetermined number of elements shared by the plurality of pixels, the predetermined number of elements being for outputting a pixel signal at a level corresponding to the charge, wherein one or some of the plurality of pixels is/are a correction pixel(s) outputting a correction pixel signal used for correcting a pixel signal outputted from pixels other than the one or some of the plurality of pixels, and one or some of the predetermined number of elements is/are formed on a wiring layer side of the light receiving parts included in the correction pixel(s).
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: July 27, 2021
    Assignee: Sony Corporation
    Inventor: Yorito Sakano
  • Publication number: 20210211599
    Abstract: An imaging apparatus of the present disclosure includes: a first switch that couples a first light-receiving device and a first charge accumulation section to each other; a second switch that couples a predetermined node and the first charge accumulation section to each other; a third switch that applies a predetermined voltage to the predetermined node; a fourth switch that couples a second light-receiving device and a second charge accumulation section to each other; a fifth switch that couples the second charge accumulation section and the predetermined node to each other; an output section that outputs a pixel voltage; a driving section; and a processor that determines first to fourth values.
    Type: Application
    Filed: October 2, 2018
    Publication date: July 8, 2021
    Inventors: RYOSUKE NAKAMURA, YORITO SAKANO, ATSUSHI SUZUKI
  • Patent number: 11050955
    Abstract: The present technology relates to a solid-state imaging device, a method for driving the solid-state imaging device, and an electronic apparatus, the solid-state imaging device being capable of expanding the dynamic range without deteriorating the image quality. The solid-state imaging device includes a pixel array section having a plurality of unit pixels and a drive section. Each of the unit pixels includes a first photoelectric conversion section, a second photoelectric conversion section which is less sensitive than the first photoelectric conversion section, a charge storage section configured to store charges generated by the second photoelectric conversion section, a charge-voltage conversion section, a first transfer gate section configured to transfer charges from the first photoelectric conversion section, and a second transfer gate section configured to combine the potential of the charge-voltage conversion section with the potential of the charge storage section.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: June 29, 2021
    Assignee: SONY CORPORATION
    Inventors: Yorito Sakano, Isao Hirota, Motonobu Torii, Masaaki Takizawa, Junichiro Azami, Motohashi Yuichi, Atsushi Suzuki
  • Patent number: 11039099
    Abstract: An increase in memory capacity is suppressed in a solid-state imaging element that performs correlated double sampling processing. A pixel circuit sequentially generates each of a predetermined reset level and a plurality of signal levels corresponding to the exposure amount. An analog-to-digital converter converts a predetermined reset level into digital data and outputs the data as reset data, converts each of the plurality of pieces of signal data into digital data, and outputs the data as signal data. An arithmetic circuit holds a difference between the reset data and the signal data output first, as held data in a memory, and then adds the held data and the signal data output second and subsequent times together and causes the memory to hold the added data as new held data.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: June 15, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masaki Sakakibara, Yorito Sakano, Satoko Iida
  • Publication number: 20210143193
    Abstract: The present disclosure relates to a solid-state imaging device and an electronic apparatus which allow reduction of optical crosstalk. In an example of FIG. 5B, a charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. In an example of FIG. 5C, a charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a half (one side) of a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. By placing the charge storage unit (capacitance element) formed in the substrate in the foregoing manner between PDs which are first photoelectric conversion units, it is possible to allow the capacitance element to function as a shield pair against crosstalk between the PDs in a unit pixel.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 13, 2021
    Inventors: MASAAKI TAKIZAWA, YASUSHI TATESHITA, TAKAHIRO TOYOSHIMA, TAKUYA TOYOFUKU, YORITO SAKANO, MOTONOBU TORII
  • Patent number: 10917591
    Abstract: The present disclosure relates to a solid-state imaging device and a method of controlling a solid-state imaging device, and an electronic device for enabling appropriate expansion of a dynamic range with respect to an object moving at a high speed or an object having a large luminance difference between bright and dark to reduce motion distortion (motion artifact). Exposure of a plurality of pixels is individually controlled in units of pixels. The present disclosure can be applied to a solid-state imaging device.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: February 9, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Satoko Iida, Masaki Sakakibara, Yorito Sakano, Naosuke Asari, Masaaki Takizawa, Tomohiko Asatsuma, Shogo Furuya
  • Patent number: 10879285
    Abstract: A PD unit has a Tr-side Si/SiO2 interface formed to be p-type, and has an embedded PD. The PD, which is n-type, performs photoelectric conversion, and accumulates an electrical charge. A TG transfers the electrical charge accumulated in the PD to an FD. An Amp is connected to the FD. An RST is connected to a Reset Drain (RD), and resets the FD. An FDG is a conversion-efficiency switching switch. An FC is a MOS capacitance (gate electrode) that is connected to the FDG. A SEL selects a pixel that outputs a signal.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: December 29, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Ryoji Suzuki, Yorito Sakano
  • Patent number: 10880505
    Abstract: To reduce variations in switching timing from linear reading to logarithmic reading and perform reading with high accuracy in a solid state imaging device. A first photoelectric conversion unit converts incident light into charges and accumulates the charges in a first region. A second photoelectric conversion unit converts incident light into charges and accumulates the charges in a second region having a smaller area than the first region. A charge-voltage conversion unit accumulates charges photoelectrically converted by the first and second photoelectric conversion units for converting the charges into a voltage. First and second charge transfer units transfer charges accumulated in the first photoelectric conversion unit and charges accumulated in the second photoelectric conversion unit to the charge-voltage conversion unit, respectively. A charge reset unit resets charges accumulated in the charge-voltage conversion unit.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: December 29, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takuya Toyofuku, Yorito Sakano
  • Patent number: 10872919
    Abstract: Provided are a solid-state imaging device and an electronic apparatus that include a charge storage unit. The charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. The charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a half (one side) of a surface of the hole, and an insulating film and an upper electrode are formed so as to the hole.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: December 22, 2020
    Assignee: SONY CORPORATION
    Inventors: Masaaki Takizawa, Yasushi Tateshita, Takahiro Toyoshima, Takuya Toyofuku, Yorito Sakano, Motonobu Torii
  • Patent number: 10868056
    Abstract: The present disclosure relates to a solid-state imaging element and an electronic apparatus which are capable of utilizing almost all photoelectrically converted charges for signals during high capacitance. A pixel includes a selection transistor that is disposed on a drain side of an amplification transistor and selects a read-out row, the selection transistor selects the read-out row after reset by a reset transistor, and a transfer transistor performs reference potential read-out during high capacitance prior to reference potential read-out during low capacitance. For example, the present disclosure is applicable to a lamination-type solid-state imaging element.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 15, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yoshiaki Tashiro, Satoko Iida, Yorito Sakano
  • Publication number: 20200365629
    Abstract: To realize miniaturization of a pixel, reduction in noise, and high quantum efficiency, and to improve short-wavelength sensitivity while suppressing inter-pixel interference and variations for each pixel. According to the present disclosure, there is provided an imaging device including: a first semiconductor layer formed in a semiconductor substrate; a second semiconductor layer of a conductivity type opposite to a conductivity type of the first semiconductor layer formed on the first semiconductor layer; a pixel separation unit which defines a pixel region including the first semiconductor layer and the second semiconductor layer; a first electrode which is connected to the first semiconductor layer from one surface side of the semiconductor substrate; and a second electrode which is connected to the second semiconductor layer from a light irradiation surface side that is the other surface of the semiconductor substrate, and is formed to correspond to a position of the pixel separation unit.
    Type: Application
    Filed: August 7, 2020
    Publication date: November 19, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Jun OGI, Yoshiaki TASHIRO, Takahiro TOYOSHIMA, Yorito SAKANO, Yusuke OIKE, Hongbo ZHU, Keiichi NAKAZAWA, Yukari TAKEYA, Atsushi OKUYAMA, Yasufumi MIYOSHI, Ryosuke MATSUMOTO, Atsushi HORIUCHI
  • Patent number: 10777597
    Abstract: To realize miniaturization of a pixel, reduction in noise, and high quantum efficiency, and to improve short-wavelength sensitivity while suppressing inter-pixel interference and variations for each pixel. According to the present disclosure, there is provided an imaging device including: a first semiconductor layer formed in a semiconductor substrate; a second semiconductor layer of a conductivity type opposite to a conductivity type of the first semiconductor layer formed on the first semiconductor layer; a pixel separation unit which defines a pixel region including the first semiconductor layer and the second semiconductor layer; a first electrode which is connected to the first semiconductor layer from one surface side of the semiconductor substrate; and a second electrode which is connected to the second semiconductor layer from a light irradiation surface side that is the other surface of the semiconductor substrate, and is formed to correspond to a position of the pixel separation unit.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: September 15, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Jun Ogi, Yoshiaki Tashiro, Takahiro Toyoshima, Yorito Sakano, Yusuke Oike, Hongbo Zhu, Keiichi Nakazawa, Yukari Takeya, Atsushi Okuyama, Yasufumi Miyoshi, Ryosuke Matsumoto, Atsushi Horiuchi