Abstract: A semiconductor memory device includes first to fourth resistance change elements sequentially arranged apart from each other in a first direction, a first electrode which connects one terminals of the first and second resistance change elements, a second electrode which connects one terminals of the third and fourth resistance change elements, a bit line which connects the other terminals of the second and third resistance change elements, first to fourth word lines respectively paired with the first to fourth resistance change elements, arranged apart from the first and second electrodes, and running in a second direction, a first current source which supplies a first electric current to a chain structure, when writing data in a selected element, and a second current source which supplies a second electric current to a selected word line which corresponds to the selected element, when writing the data in the selected element.

Abstract: A semiconductor memory device includes first to third wiring layers formed above a semiconductor substrate, extending in a first direction, and sequentially arranged in a second direction perpendicular to the first direction, a plurality of active areas formed in the semiconductor substrate, and extending in a direction oblique to the first direction, first and second selection transistors formed in each of the active areas, and sharing a source region electrically connected to the second wiring layer, a first magnetoresistive element having one terminal electrically connected to a drain region of the first selection transistor, and the other terminal electrically connected to the first wiring layer, and a second magnetoresistive element having one terminal electrically connected to a drain region of the second selection transistor, and the other terminal electrically connected to the third wiring layer.

Abstract: A magnetoresistive element includes a stack formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed, a first nonmagnetic layer, a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, a first circumferential wall provided on the second nonmagnetic layer in contact with a circumferential surface of the second fixed layer to surround the second fixed layer, and made of an insulator, and a second circumferential wall provided on the first nonmagnetic layer in contact with a circumferential surface of the free layer to surround the free layer, and made of an insulator.

Abstract: A semiconductor memory device includes first and second bit line provided in the same level layer above a semiconductor substrate, a first variable-resistance element disposed under the first bit line, having one terminal connected to one end of a current path of a first MOSFET, a second variable-resistance element disposed under the second bit line, and having one terminal connected to one end of a current path of a second MOSFET, a first interconnect layer connecting the first bit line to the other terminal of the first variable-resistance element, and connecting the first bit line to the other end of the current path of the second MOSFET, and a second interconnect layer connecting the second bit line to the other terminal of the second variable-resistance element, and connecting the second bit line to the other end of the current path of the first MOSFET.

Abstract: A magnetoresistive element includes a stacked structure including a fixed layer having a fixed direction of magnetization, a recording layer having a variable direction of magnetization, and a nonmagnetic layer sandwiched between the fixed layer and the recording layer, a first protective film covering a circumferential surface of the stacked structure, and made of silicon nitride, and a second protective film covering a circumferential surface of the first protective film, and made of silicon nitride. A hydrogen content in the first protective film is not more than 4 at %, and a hydrogen content in the second protective film is not less than 6 at %.

Abstract: A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.

Abstract: A magnetic memory includes an interlayer insulation layer provided on a substrate, a conductive underlying layer provided on the interlayer insulation layer, and a magnetoresistive element provided on the underlying layer and including two magnetic layers and a nonmagnetic layer interposed between the magnetic layers. The underlying layer has an etching rate lower than an etching rate of each of the magnetic layers.

Abstract: A resistance-change memory includes an interlayer insulating film, a lower electrode layer, a fixed layer, a first insulating film, a recording layer, a second insulating film, a conducting layer and an interconnect. The interlayer insulating film is formed on a semiconductor substrate and has a step. The lower electrode layer is formed on the interlayer insulating film including the step. The fixed layer is formed on the lower electrode layer and has invariable magnetization. The first insulating film is formed on the fixed layer. The recording layer is formed on part of the first insulating film and has variable magnetization. The second insulating film is over the recording layer and in contact with the first insulating film. The conducting layer is formed on the second insulating film. The interconnect is connected to the conducting layer.

Abstract: A magnetoresistive element includes a stack formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed, a first nonmagnetic layer, a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, a first circumferential wall provided on the second nonmagnetic layer in contact with a circumferential surface of the second fixed layer to surround the second fixed layer, and made of an insulator, and a second circumferential wall provided on the first nonmagnetic layer in contact with a circumferential surface of the free layer to surround the free layer, and made of an insulator.

Abstract: A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.

Abstract: A semiconductor memory of an aspect of the present invention including a main bit line, a first and second sub-bit line, a first resistive memory element which has a first terminal being connected with the main bit line, a first select transistor which has one end of a first current path being connected with the second terminal of the first resistive memory element and the other end of the first current path being connected with the first sub-bit line, a second resistive memory element which has a third terminal being connected with the main bit line, and a second select transistor which has one end of a second current path being connected with the fourth terminal of the second resistive memory element and the other end of the second current path being connected with the second sub-bit line.

Abstract: A resistance change memory includes a first interconnection, a second interconnection, a first resistance change element which has a first electrode, a second electrode, and a first tunnel insulating film provided between the first electrode and the second electrode, the first tunnel insulating film including a first trap region formed by introducing defects to trap holes or electrons, and the second electrode being connected to the first interconnection, and a first transistor whose current path has one end connected to the first electrode and the other end connected to the second interconnection.

Abstract: A semiconductor memory device includes n resistance change elements which are arranged in one cell, have a low-resistance state and a high resistance state, are connected in series or parallel, have different resistance values in the same resistance state, and change between the low-resistance state and the high-resistance state under different conditions, and a write circuit which is connected to one end of the n resistance change elements, and applies a pulse current m (1?m?n) times to the n resistance change elements during a write operation. Letting Im be a current value of an mth pulse current, condition I1>I2> . . . >Im holds.

Abstract: A semiconductor memory according to an embodiment of the present invention including first and second adjacent bit lines extending in a first direction and provided in the same interconnect layer, an active provided in a memory cell array, a first and second adjacent word lines extending in a second direction intersecting the first direction, a cell group having two transistor provided in the active region and two resistive storage element, wherein the active region has a striped structure, and extends from one end of the memory cell array to the other.

Abstract: A magnetic random access memory includes a semiconductor substrate having a projection projecting from a substrate surface, first and second gate electrodes and a first source diffusion layer formed on first and second side surfaces and an upper surface of the projection, first and second drain diffusion layers formed in the substrate surface at roots on the first and second side surfaces of the first projection, first and second word lines formed above the semiconductor substrate, a bit line formed above the first and second word lines, a first magnetoresistive effect element formed between the bit line and the first word line, a second magnetoresistive effect element formed between the bit line and the second word line, a first contact which connects the first magnetoresistive effect element and the first drain diffusion layer, and a second contact which connects the second magnetoresistive effect element and the second drain diffusion layer.

Abstract: A resistance change type memory includes first, second and third drive lines, a resistance change element having one end connected to the third drive line, a first diode having an anode connected to the first drive line and a cathode connected to other end of the first resistance change element, a second diode having an anode connected to other end of the first resistance change element and a cathode connected to the second drive line, and a driver/sinker which supplies a write current to the resistance change element. A write control circuit is arranged such that when first data is written, the write current is caused to flow in a direction from the first drive line to the third drive line, and when second data is written, the write current is caused to flow in a direction from the third drive line to the second drive line.

Abstract: A semiconductor memory device comprising: a support substrate; an insulating film formed on the support substrate; a semiconductor film formed on the insulating film; a gate insulating film formed on the semiconductor film; a gate electrode film formed on the gate insulating film; and a source region and a drain region formed in the semiconductor film so as to sandwich the gate insulating film in a gate length direction, the source and drain regions contacting the insulating film at the bottom surface, and the semiconductor memory device storing data corresponding to the amount of charges accumulated in the semiconductor film surrounded by the insulating film, the gate insulating film, and the source and drain regions and electrically floated, wherein a border length between the source region and the gate insulating film contiguous to each other is different from a border length between the drain region and the gate insulating film to each other.

Abstract: A semiconductor memory device includes a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data. An allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched when a power source is turned on.

Abstract: A semiconductor memory device includes a bit line which is provided above a semiconductor substrate and runs in a first direction, a source line which is provided above the semiconductor substrate and runs in the first direction, an active area which is provided in the semiconductor substrate and extends in the first direction, first and second selection transistors which are formed on the active area and share a source region electrically connected to the source line, a first memory element having one end electrically connected to a drain region of the first selection transistor and the other end electrically connected to the bit line, and a second memory element having one end electrically connected to a drain region of the second selection transistor and the other end electrically connected to the bit line.

Abstract: A magnetoresistive element includes a first electrode layer, a first fixed layer provided on the first electrode layer and having a fixed magnetization direction, a first intermediate layer provided on the first fixed layer and made of a metal oxide, a free layer provided on the first intermediate layer and having a variable magnetization direction, and a second electrode layer provided on the free layer. At least one of the first electrode layer and the second electrode layer contains a conductive metal oxide.