Abstract: A semiconductor device comprising a semiconductor substrate, a switching element which is provided on the semiconductor substrate, a first interconnect layer which is provided above the semiconductor substrate, a plurality of phase-change memory devices which have phase-change material whose resistance changes by a phase-change due to a temperature change, being stacked, and being connected in series to the first interconnect layer and the switching element, a plurality of first heating elements which are connected in series to the respective phase-change memory devices, and a plurality of second heating elements which are connected to second interconnect layers different from the first interconnect layer, and which are provided so as to correspond to the respective phase-change memory devices.

Abstract: A semiconductor memory device includes a memory cell block including a plurality of memory cells connected in series between first node and second node, the memory cells including a magnetoresistive element and a switching transistor, which are connected in parallel, the magnetoresistive element being a spin injection type and including a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction changes, and a non-magnetic layer interposed between the fixed layer and the recording layer, a bit line connected to the first node via a selection transistor, a word line connected to a gate of the switching transistor, and a write line connected to the second node.

Abstract: A semiconductor integrated circuit device comprises magneto-resistive elements, bit lines electrically connected to the magneto-resistive elements at an end of the latter, read word lines electrically connected to the magneto-resistive elements at the other end of the latter and write word lines. The write word lines are insulated from the magneto-resistive elements and adapted to apply a magnetic field to selected magneto-resistive elements at the time of writing data to the selected magneto-resistive elements.

Abstract: A data selection line (write line) is disposed right on a MTJ element. Upper and side surfaces of the data selection line are coated with yoke materials which have a high permeability. The yoke materials are separated from each other by a barrier layer. Similarly, a write word line is disposed right under the MTJ element. The lower and side surfaces of the write word line are also coated with the yoke materials which have the high permeability. The yoke materials on the lower and side surfaces of the write word line are also separated from each other by the barrier layer.

Abstract: A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.

Abstract: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.

Abstract: A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.

Abstract: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.

Abstract: A magnetic memory device includes an SOI substrate having a first semiconductor layer, a first insulating film formed on the first semiconductor layer, and a second semiconductor layer formed on the first insulating film, an element isolation insulating film formed selectively in the second semiconductor layer extending from a surface of the second semiconductor layer with a depth reaching the first insulating film, a switching element formed in the second semiconductor layer, a magneto-resistive element connected to the switching element, a first wiring extending in a first direction at a distance below the magneto-resistive element, and a second wiring formed on the magneto-resistive element and extending in a second direction different from the first direction.

Abstract: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.

Abstract: A write wiring for writing information in an MTJ device is covered with a magnetic layer. The magnetic layer has a structure in which the growing direction of columnar grains is 300 or less from the normal-line direction of sidewalls, a structure in which grains are deposited like a layer, or a structure in which grains are amorphously deposited.

Abstract: A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.

Abstract: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.

Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.

Abstract: A semiconductor integrated circuit device includes a cell transistor; a bit line provided above the cell transistor; a magnetoresistive element provided above the bit line, a first end portion of the magnetoresistive element being electrically connected to the bit line; an intracell local interconnection provided above the magnetoresistive element, the intracell local interconnection coupling one of source and drain regions of the cell transistor to a second end portion of the magnetoresistive element; and a write word line provided above the intracell local interconnection, a portion between the write word line and the intracell local interconnection being filled with an insulator alone.

Abstract: A write wiring for writing information in an MTJ device is covered with a magnetic layer. The magnetic layer has a structure in which the growing direction of columnar grains is 30° or less from the normal-line direction of sidewalls, a structure in which grains are deposited like a layer, or a structure in which grains are amorphously deposited.

Abstract: A magnetic memory device includes an SOI substrate having a first semiconductor layer, a first insulating film formed on the first semiconductor layer, and a second semiconductor layer formed on the first insulating film, an element isolation insulating film formed selectively in the second semiconductor layer extending from a surface of the second semiconductor layer with a depth reaching the first insulating film, a switching element formed in the second semiconductor layer, a magneto-resistive element connected to the switching element, a first wiring extending in a first direction at a distance below the magneto-resistive element, and a second wiring formed on the magneto-resistive element and extending in a second direction different from the first direction.

Abstract: A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.

Abstract: A magnetic random access memory includes memory cells each including a TMR element and a selection element, and a read circuit which reads storage information from the TMR element by applying read voltage to a selected one of the memory cells and causing a current to flow through the TMR element via the selection element. The read circuit includes a voltage setting section used to apply voltage which makes a resistance variation rate of the TMR element substantially equal to half a resistance variation rate thereof obtained when 0 V is applied across the TMR element to the TMR element at the information read time.

Abstract: A highly reliable magnetic memory exhibits enhanced data-holding stability at high storage density in a storage layer of a magnetoresistive effect element used for memory cells. A magnetic memory includes a memory cell array having first wirings, second wirings intersecting the first wirings and memory cells each provided at an intersection area of the corresponding first and second wirings. Each memory cell is selected when the corresponding first and second wirings are selected.