Patents by Inventor Yoshiaki Asao

Yoshiaki Asao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7505306
    Abstract: A magnetic memory device includes a magnetization fixed layer provided above a semiconductor substrate surface and having a fixed magnetization direction. A first magnetization free layer is provided above the magnetization fixed layer, has variable magnetization direction, and has an easy magnetization axis extending along a plane intersecting the substrate surface and along a direction neither parallel nor perpendicular to the substrate surface. A second magnetization free layer is provided above the first magnetization free layer, has a magnetization that antiferromagnetically couples with the first magnetization free layer. A first write line is placed above and electrically connected to the second magnetization free layer, and extends in a direction that pierces the plane. A second write line faces the first and/or second magnetization free layer, and extends along the substrate surface and the plane and in a direction perpendicular to the first write line.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: March 17, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Toshihiko Nagase, Yoshiaki Asao
  • Publication number: 20080308887
    Abstract: A semiconductor memory device includes first to third wiring layers formed above a semiconductor substrate, extending in a first direction, and sequentially arranged in a second direction perpendicular to the first direction, a plurality of active areas formed in the semiconductor substrate, and extending in a direction oblique to the first direction, first and second selection transistors formed in each of the active areas, and sharing a source region electrically connected to the second wiring layer, a first magnetoresistive element having one terminal electrically connected to a drain region of the first selection transistor, and the other terminal electrically connected to the first wiring layer, and a second magnetoresistive element having one terminal electrically connected to a drain region of the second selection transistor, and the other terminal electrically connected to the third wiring layer.
    Type: Application
    Filed: November 21, 2007
    Publication date: December 18, 2008
    Inventors: Yoshiaki Asao, Takeshi Kajiyama
  • Publication number: 20080265347
    Abstract: A magnetoresistive element includes a first stacked structure formed by sequentially stacking a first fixed layer in which a magnetization direction is fixed and a first nonmagnetic layer, a second stacked structure formed on the first stacked structure by sequentially stacking a free layer in which a magnetization direction is changeable, a second nonmagnetic layer, and a second fixed layer in which a magnetization direction is fixed, and a circumferential wall formed in contact with a circumferential surface of the second stacked structure to surround the second stacked structure, and made of an insulator. A circumferential surface of the first stacked structure is substantially perpendicular. The second stacked structure has a tapered shape which narrows upward.
    Type: Application
    Filed: April 23, 2008
    Publication date: October 30, 2008
    Inventors: Masayoshi Iwayama, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani
  • Publication number: 20080239782
    Abstract: A semiconductor memory device includes a bit line which is provided above a semiconductor substrate and runs in a first direction, a source line which is provided above the semiconductor substrate and runs in the first direction, an active area which is provided in the semiconductor substrate and extends in the first direction, first and second selection transistors which are formed on the active area and share a source region electrically connected to the source line, a first memory element having one end electrically connected to a drain region of the first selection transistor and the other end electrically connected to the bit line, and a second memory element having one end electrically connected to a drain region of the second selection transistor and the other end electrically connected to the bit line.
    Type: Application
    Filed: September 26, 2007
    Publication date: October 2, 2008
    Inventor: Yoshiaki ASAO
  • Publication number: 20080225577
    Abstract: A magnetic random access memory includes a bit line running in a first direction, a first word line running in a second direction different from the first direction, and a memory element having a magnetoresistive effect element including a fixed layer having a fixed magnetization direction, a recording layer having a reversible magnetization direction, and a nonmagnetic layer formed between the fixed layer and the recording layer, the magnetization directions in the fixed layer and the recording layer being perpendicular to a film surface, and a heater layer in contact with the magnetoresistive effect element, the memory element being connected to the bit line, and formed to oppose a side surface of the first word line such that the memory element is insulated from the first word line.
    Type: Application
    Filed: March 6, 2008
    Publication date: September 18, 2008
    Inventors: Keiji HOSOTANI, Yoshiaki Asao, Toshihiko Nagase
  • Publication number: 20080204944
    Abstract: It is possible to reduce writing current without causing fluctuation of the writing characteristic. A magnetic memory includes: a magnetoresistance effect element having a magnetization pinned layer whose magnetization direction is pinned, a storage layer whose magnetization direction is changeable, and a non-magnetic layer provided between the magnetization pinned layer and the storage layer; and a first wiring layer which is electrically connected to the magnetoresistance effect element and extends in a direction substantially perpendicular to a direction of an easy magnetization axis of the storage layer, an end face of the magnetoresistance effect element substantially perpendicular to the direction of the easy magnetization axis of the storage layer and an end face of the first wiring layer substantially perpendicular to the direction of the easy magnetization axis being positioned on the same plane.
    Type: Application
    Filed: April 10, 2008
    Publication date: August 28, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao, Hiroaki Yoda
  • Publication number: 20080203503
    Abstract: A magnetic random access memory includes a first bit line and a second bit line, a source line formed for a group having the first bit line and the second bit line, adjacent to the first bit line, and running in a first direction in which the first bit line and the second bit line run, a first magnetoresistive effect element connected to the first bit line, a second magnetoresistive effect element connected to the second bit line, a first transistor connected in series with the first magnetoresistive effect element, and a second transistor connected in series with the second magnetoresistive effect element. A first cell having the first magnetoresistive effect element and the first transistor and a second cell having the second magnetoresistive effect element and the second transistor are connected together to the source line.
    Type: Application
    Filed: January 30, 2008
    Publication date: August 28, 2008
    Inventor: Yoshiaki ASAO
  • Publication number: 20080205126
    Abstract: A magnetic random access memory which is a memory cell array including a magnetoresistive effect element having a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction is reversible, and a non-magnetic layer provided between the fixed layer and the recording layer, wherein all conductive layers in the memory cell array arranged below the magnetoresistive effect element are formed of materials each containing an element selected from a group including W, Mo, Ta, Ti, Zr, Nb, Cr, Hf, V, Co, and Ni.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 28, 2008
    Inventors: Takeshi Kajiyama, Yoshiaki Asao
  • Publication number: 20080206895
    Abstract: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.
    Type: Application
    Filed: April 24, 2008
    Publication date: August 28, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki ASAO, Hiroaki YODA
  • Patent number: 7414879
    Abstract: A semiconductor memory device includes a memory cell block including a plurality of memory cells connected in series between first node and second node, the memory cells including a magnetoresistive element and a switching transistor, which are connected in parallel, the magnetoresistive element being a spin injection type and including a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction changes, and a non-magnetic layer interposed between the fixed layer and the recording layer, a bit line connected to the first node via a selection transistor, a word line connected to a gate of the switching transistor, and a write line connected to the second node.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: August 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Akihiro Nitayama
  • Publication number: 20080170432
    Abstract: A magnetic random access memory includes a memory cell element which includes a first fixed layer, a first recording layer in which a magnetization direction reverses on the basis of a first threshold value, and a first nonmagnetic layer formed between the first fixed layer and the first recording layer, a first interconnection connected to one terminal of the memory cell element, a transistor whose current path has one end connected to the other terminal of the memory cell element, a second interconnection connected to the other end of the current path, and a first resistance change element electrically connected to the memory cell element, and having a resistance value which changes on the basis of a second threshold value.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 17, 2008
    Inventor: Yoshiaki ASAO
  • Publication number: 20080151608
    Abstract: A semiconductor memory device includes first to fourth resistance change elements sequentially arranged apart from each other in a first direction, a first electrode which connects one terminals of the first and second resistance change elements, a second electrode which connects one terminals of the third and fourth resistance change elements, a bit line which connects the other terminals of the second and third resistance change elements, first to fourth word lines respectively paired with the first to fourth resistance change elements, arranged apart from the first and second electrodes, and running in a second direction, a first current source which supplies a first electric current to a chain structure, when writing data in a selected element, and a second current source which supplies a second electric current to a selected word line which corresponds to the selected element, when writing the data in the selected element.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 26, 2008
    Inventors: Keiji HOSOTANI, Yoshiaki Asao
  • Publication number: 20080135958
    Abstract: A magnetic random access memory includes a magnetoresistive effect element which has a fixed layer, a recording layer and a non-magnetic layer provided between the fixed layer and the recording layer and in which the magnetization directions of the fixed layer and the recording layer are brought into a parallel state or an anti-parallel state in accordance with a direction of a current flowing between the fixed layer and the recording layer, a first contact which is connected to the recording layer and in which a contact area between the recording layer and the first contact is smaller than an area of the recording layer, and a cap layer which is provided between the first contact and the recording layer and which directly comes in contact with the first contact and which has a resistance higher than a resistance of the recording layer.
    Type: Application
    Filed: November 20, 2007
    Publication date: June 12, 2008
    Inventors: Takeshi KAJIYAMA, Yoshiaki Asao, Akihiro Nitayama
  • Patent number: 7376003
    Abstract: A magnetic field H1 in the hard-axis direction and a magnetic field H2 in the easy-axis direction are caused to simultaneously act on a MTJ element having an ideal asteroid curve, thereby reversing the magnetizing direction of the storing layer of the MTJ element. When the actual asteroid curve shifts in the hard-axis direction by Ho, a corrected synthesized magnetic field ({right arrow over (H1)}+{right arrow over (H2)}+{right arrow over (Ho)}) is generated in write operation to reliably reverse the magnetizing direction. The corrected synthesized magnetic field can easily be generated by individually controlling a write word/bit line current on the basis of programmed setting data.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: May 20, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Yoshiaki Asao, Kentaro Nakajima
  • Patent number: 7372118
    Abstract: A magnetic random access memory includes, a lower electrode, a magnetoresistive element which is arranged above the lower electrode and has side surfaces, and a protective film which covers the side surfaces of the magnetoresistive element, has a same planar shape as the lower electrode, and is formed by one of sputtering, plasma CVD, and ALD.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Hiroaki Yoda
  • Publication number: 20080080233
    Abstract: A magnetic random access memory includes a first wiring, a second wiring formed above and spaced apart from the first wiring, a magnetoresistive effect element formed between the first wiring and the second wiring, formed in contact with an upper surface of the first wiring, and having a fixed layer, a recording layer, and a nonmagnetic layer formed between the fixed layer and the recording layer, a metal layer formed on the magnetoresistive effect element and integrated with the magnetoresistive effect element to form stacked layers, a first side insulating film formed on side surfaces of the metal layer, the magnetoresistive effect element, and the first wiring, a first contact formed in contact with a side surface of the first side insulating film, and a third wiring formed on the metal layer and the first contact to electrically connect the magnetoresistive effect element and the first contact.
    Type: Application
    Filed: August 15, 2007
    Publication date: April 3, 2008
    Inventors: Keiji Hosotani, Yoshiaki Asao, Akihiro Nitayama
  • Patent number: 7333359
    Abstract: A write word line is disposed right under a MTJ element. The write word line extends in an X direction, and side and lower surfaces of the write word line are coated with a hard magnetic material and yoke material. The hard magnetic material is magnetized by a surplus current passed through the write word line, and a characteristic of the MTJ element is corrected by residual magnetization. A data selection line (read/write bit line) is disposed right on the MTJ element. The data selection line extends in a Y direction intersecting with the X direction, and a part of the surface of the data selection line is coated with the yoke material.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: February 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Yoshihisa Iwata, Yoshiaki Saito, Hiroaki Yoda, Tomomasa Ueda, Minoru Amano, Shigeki Takahashi, Tatsuya Kishi
  • Publication number: 20080035958
    Abstract: A magnetic random access memory includes a semiconductor substrate having a projection projecting from a substrate surface, first and second gate electrodes and a first source diffusion layer formed on first and second side surfaces and an upper surface of the projection, first and second drain diffusion layers formed in the substrate surface at roots on the first and second side surfaces of the first projection, first and second word lines formed above the semiconductor substrate, a bit line formed above the first and second word lines, a first magnetoresistive effect element formed between the bit line and the first word line, a second magnetoresistive effect element formed between the bit line and the second word line, a first contact which connects the first magnetoresistive effect element and the first drain diffusion layer, and a second contact which connects the second magnetoresistive effect element and the second drain diffusion layer.
    Type: Application
    Filed: August 3, 2007
    Publication date: February 14, 2008
    Inventor: Yoshiaki Asao
  • Publication number: 20080002459
    Abstract: A magnetic memory device includes a magnetization fixed layer provided above a semiconductor substrate surface and having a fixed magnetization direction. A first magnetization free layer is provided above the magnetization fixed layer, has variable magnetization direction, and has an easy magnetization axis extending along a plane intersecting the substrate surface and along a direction neither parallel nor perpendicular to the substrate surface. A second magnetization free layer is provided above the first magnetization free layer, has a magnetization that antiferromagnetically couples with the first magnetization free layer. A first write line is placed above and electrically connected to the second magnetization free layer, and extends in a direction that pierces the plane. A second write line faces the first and/or second magnetization free layer, and extends along the substrate surface and the plane and in a direction perpendicular to the first write line.
    Type: Application
    Filed: December 12, 2006
    Publication date: January 3, 2008
    Inventors: Yoshiaki FUKUZUMI, Toshihiko Nagase, Yoshiaki Asao
  • Patent number: 7277318
    Abstract: A write wiring for writing information in an MTJ device is covered with a magnetic layer. The magnetic layer has a structure in which the growing direction of columnar grains is 30° or less from the normal-line direction of sidewalls, a structure in which grains are deposited of sidewalls, a structure in which grains are deposited like a layer, or a structure in which grains are amorphously deposited.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: October 2, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yoda, Hisanori Aikawa, Tomomasa Ueda, Tatsuya Kishi, Takeshi Kajiyama, Yoshiaki Asao