Patents by Inventor Yoshiaki Nakayama

Yoshiaki Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10761142
    Abstract: A battery monitoring unit includes a plurality of voltage detection lines, a flexible printed circuit board extending in a stuck direction of single batteries, an electronic circuit connected to one end portions of the plurality of the voltage detection lines so as to detect voltage of each of the single batteries and mounted on the flexible printed circuit board, a plurality of busbar fixing portions formed integrally with the flexible printed circuit board and to which the plurality of the busbars are fixed respectively, and communication lines disposed in the flexible printed circuit board so as to connect between the electronic circuit and a battery ECU.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: September 1, 2020
    Assignee: YAZAKI CORPORATION
    Inventors: Takao Ota, Kazuya Harakawa, Yoshiaki Ichikawa, Yoshiaki Nakayama
  • Patent number: 10707729
    Abstract: The present invention is a structure of an electrical connection portion formed by thermal bonding of a terminal 53 of a current-carrying component 50 of a motor and a winding wire 30. The terminal 53 includes a lock portion 53a positioned on a base end side and a fusion portion 53b positioned on a distal end side. The winding wire 30 includes a binding portion 31 wound around the lock portion 53a and has a one end portion 36 coupled to a molten ball 55 generated at the fusion portion 53b; and a coupling wire portion 33 tightly stretched from a main winding wire portion 34 of the motor disposed in a wound state and continuous to the other end portion of the binding portion 31. The one end portion 36 of the binding portion 31 is in a state where tension pulling the coupling wire portion 33 to the main winding wire portion 34 side does not act.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 7, 2020
    Assignee: MABUCHI MOTOR CO., LTD.
    Inventors: Shou Nakayama, Yoshiaki Maeda, Takeshi Hirano, Kenji Muneda, Keishirou Maki
  • Publication number: 20200203435
    Abstract: A solid-state imaging device includes a first electrode, a second electrode, and a photoelectric conversion film that is formed between the first electrode and the second electrode and includes an organic semiconductor and an inorganic material.
    Type: Application
    Filed: March 3, 2020
    Publication date: June 25, 2020
    Inventors: NORIKAZU NAKAYAMA, HIDEKI ONO, YOSHIAKI OBANA, NOBUYUKI MATSUZAWA
  • Patent number: 10608050
    Abstract: A solid-state imaging device includes a first electrode, a second electrode, and a photoelectric conversion film that is formed between the first electrode and the second electrode and includes an organic semiconductor and an inorganic material.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: March 31, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Norikazu Nakayama, Hideki Ono, Yoshiaki Obana, Nobuyuki Matsuzawa
  • Publication number: 20200006435
    Abstract: A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer provided between the first electrode and the second electrode, and including a first organic semiconductor material, a second organic semiconductor material, and a third organic semiconductor material that have mother skeletons different from one another. The first organic semiconductor material is one of fullerenes and fullerene derivatives. The second organic semiconductor material in a form of a single-layer film has a higher linear absorption coefficient of a maximal light absorption wavelength in a visible light region than a single-layer film of the first organic semiconductor material and a single-layer film of the third organic semiconductor material. The third organic semiconductor material has a value equal to or higher than a HOMO level of the second organic semiconductor material.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 2, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yuta HASEGAWA, Nobuyuki MATSUZAWA, Yoshiaki OBANA, Ichiro TAKEMURA, Norikazu NAKAYAMA, Masami SHIMOKAWA, Tetsuji YAMAGUCHI, Iwao YAGI, Hideaki MOGI
  • Patent number: 10497489
    Abstract: A cable includes a conductor, an insulation coating layer on the conductor, and an outer coating layer on the insulation coating layer. The insulation coating layer is made of a composition containing 100 parts by mass of a base polymer (A) and 100 to 250 parts by mass of a non-halogen flame retardant. The polymer (A) contains 70% to 99% by mass of an ethylene-vinyl acetate copolymer (a1) containing an ethylene-vinyl acetate copolymer having a melting point of 70° C. or higher, and 1% to 30% by mass of an acid-modified polyolefin resin (a2) having a glass transition point of ?55° C. or lower. The polymer (A) contains 25% to 50% by mass of a vinyl acetate component derived from the copolymer (a1). The outer coating layer is made of a composition containing 100 parts by mass of a base polymer (B) and 150 to 220 parts by mass of a non-halogen flame retardant.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 3, 2019
    Assignee: HITACHI METALS, LTD.
    Inventors: Makoto Iwasaki, Motoharu Kajiyama, Yoshiaki Nakamura, Hiroshi Okikawa, Mitsuru Hashimoto, Kenichiro Fujimoto, Akinari Nakayama
  • Publication number: 20190325967
    Abstract: A data erasure device is for a non-volatile semiconductor memory device, which includes cells in which data is written by an application of a first voltage and erased by an application of a second voltage differing from the first voltage. The data erasure device includes a controller. The controller the controller applies a second voltage to the cells over first time period with multiple occurrences to set the cells into a first erasure state, and applies the second voltage to the cells over second time period, which is longer than the first time period, to set the cells in a second erasure state deeper than the first erasure state. The controller changes a number of occurrences of applying the second voltage over the first time period to each of the cells or each of multiple cell groups having the cells according to respective erasure states of the cells.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Koichi YAKO, Yoshiaki NAKAYAMA
  • Publication number: 20190296149
    Abstract: In a semiconductor device, a trench is continuously connected to reach a main cell region and a sense cell region, and a shield electrode and a gate electrode layer are continuously connected to reach the main cell region and the sense cell region within the trench. The shield electrode extends to a side of the main cell region away from the sense cell region on one end side of the trench in a longitudinal direction to be electrically connected to an upper electrode. The gate electrode layer extends to a side of the main cell region away from the sense cell region on the other end side of the trench in the longitudinal direction to be electrically connected to a gate liner.
    Type: Application
    Filed: June 12, 2019
    Publication date: September 26, 2019
    Inventors: Tsuyoshi YAMAMOTO, Kenta GODA, Shunsuke HARADA, Yoshiaki NAKAYAMA
  • Patent number: 10424947
    Abstract: A battery monitoring device includes a battery information input terminal, a battery state monitoring unit, an output terminal, a circuit board, and a housing member. The battery information input terminal is electrically connected to a battery state detecting member. The battery state monitoring unit receives a battery state detection signal via the battery information input terminal. The output terminal outputs monitoring information on the battery state corresponding to the battery state detection signal to an external arithmetic processor. The circuit board is provided with the battery information input terminal, the battery state monitoring unit, and the output terminal. The housing member is integrally formed with the battery information input terminal, the battery state monitoring unit, the output terminal, and the circuit board so as to accommodate at least the whole battery state monitoring unit and the whole circuit board and expose terminal connecting portions to the outside.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: September 24, 2019
    Assignee: YAZAKI CORPORATION
    Inventors: Yuki Chiyajo, Yoshiaki Nakayama, Kimihiro Matsuura, Haruhiko Yoshida
  • Patent number: 10374015
    Abstract: A photoelectric conversion element according to an embodiment of the present disclosure includes: a first electrode and a second electrode facing each other; and a photoelectric conversion layer provided between the first electrode and the second electrode, and including a first organic semiconductor material, a second organic semiconductor material, and a third organic semiconductor material that have mother skeletons different from one another. The first organic semiconductor material is one of fullerenes and fullerene derivatives. The second organic semiconductor material in a form of a single-layer film has a higher linear absorption coefficient of a maximal light absorption wavelength in a visible light region than a single-layer film of the first organic semiconductor material and a single-layer film of the third organic semiconductor material. The third organic semiconductor material has a value equal to or higher than a HOMO level of the second organic semiconductor material.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: August 6, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yuta Hasegawa, Nobuyuki Matsuzawa, Yoshiaki Obana, Ichiro Takemura, Norikazu Nakayama, Masami Shimokawa, Tetsuji Yamaguchi, Iwao Yagi, Hideaki Mogi
  • Publication number: 20180233930
    Abstract: A battery monitoring device includes a battery information input terminal, a battery state monitoring unit, an output terminal, a circuit board, and a housing member. The battery information input terminal is electrically connected to a battery state detecting member. The battery state monitoring unit receives a battery state detection signal via the battery information input terminal. The output terminal outputs monitoring information on the battery state corresponding to the battery state detection signal to an external arithmetic processor. The circuit board is provided with the battery information input terminal, the battery state monitoring unit, and the output terminal. The housing member is integrally formed with the battery information input terminal, the battery state monitoring unit, the output terminal, and the circuit board so as to accommodate at least the whole battery state monitoring unit and the whole circuit board and expose terminal connecting portions to the outside.
    Type: Application
    Filed: January 12, 2018
    Publication date: August 16, 2018
    Applicant: Yazaki Corporation
    Inventors: Yuki CHIYAJO, Yoshiaki NAKAYAMA, Kimihiro MATSUURA, Haruhiko YOSHIDA
  • Publication number: 20180088179
    Abstract: A battery monitoring unit includes a plurality of voltage detection lines, a flexible printed circuit board extending in a stuck direction of single batteries, an electronic circuit connected to one end portions of the plurality of the voltage detection lines so as to detect voltage of each of the single batteries and mounted on the flexible printed circuit board, a plurality of busbar fixing portions formed integrally with the flexible printed circuit board and to which the plurality of the busbars are fixed respectively, and communication lines disposed in the flexible printed circuit board so as to connect between the electronic circuit and a battery ECU.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 29, 2018
    Inventors: Takao Ota, Kazuya Harakawa, Yoshiaki Ichikawa, Yoshiaki Nakayama
  • Patent number: 8604513
    Abstract: A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: December 10, 2013
    Assignee: DENSO CORPORATION
    Inventors: Youichi Ashida, Norihito Tokura, Shigeki Takahashi, Yoshiaki Nakayama, Satoshi Shiraki, Kouji Senda
  • Publication number: 20110073904
    Abstract: A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 31, 2011
    Applicant: DENSO CORPORATION
    Inventors: Youichi Ashida, Norihito Tokura, Shigeki Takahashi, Yoshiaki Nakayama, Satoshi Shiraki, Kouji Senda
  • Patent number: 7799667
    Abstract: A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: September 21, 2010
    Assignee: DENSO CORPORATION
    Inventors: Satoshi Shiraki, Yoshiaki Nakayama, Shoji Mizuno, Takashi Nakano, Akira Yamada
  • Publication number: 20090096799
    Abstract: A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit.
    Type: Application
    Filed: December 24, 2008
    Publication date: April 16, 2009
    Applicant: Hitachi, Ltd.
    Inventors: Yoshiaki Nakayama, Nobuaki Kabuto, Yohei Kato
  • Publication number: 20090096800
    Abstract: A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit.
    Type: Application
    Filed: December 24, 2008
    Publication date: April 16, 2009
    Applicant: Hitachi, Ltd.
    Inventors: Yoshiaki Nakayama, Nobuaki Kabuto, Yohei Kato
  • Publication number: 20080293202
    Abstract: A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.
    Type: Application
    Filed: July 15, 2008
    Publication date: November 27, 2008
    Applicant: DENSO CORPORATION
    Inventors: Satoshi Shiraki, Yoshiaki Nakayama, Shoji Mizuno, Takashi Nakano, Akira Yamada
  • Patent number: 7298020
    Abstract: A wire (12) is formed on an insulating film (10) on a semiconductor substrate (1). The wire (12) is covered by silicon nitride film (14), inorganic SOG film (20) and TEOS film (21). A thin film resistance element (30) of chromium silicon (CrSi) is formed on the upper surface of the TEOS film (21). The acute angle (taper angle) at which a line connecting the local maximum and minimum points of a step on the upper surface of the TEOS film (21) beneath the area where the thin film resistance element (30) is formed intersects to the surface of the substrate (1) is set to 10° or less.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: November 20, 2007
    Assignee: DENSO CORPORATION
    Inventors: Syuji Asano, Yoshiaki Nakayama, Koji Eguchi
  • Publication number: 20060086449
    Abstract: A semiconductor device comprising: an element portion having a heat generation portion; a control circuit portion having a control circuit for controlling the element portion; and a metal member. The element portion and the control circuit portion are adjacently disposed oh a surface portion of a semiconductor substrate. The metal member as an external electrode for the element portion is disposed directly on the element portion through an interlayer insulation film. The metal member is also disposed directly on the control circuit portion through the interlayer insulation film.
    Type: Application
    Filed: October 18, 2005
    Publication date: April 27, 2006
    Applicant: DENSO CORPORATION
    Inventor: Yoshiaki Nakayama