Patents by Inventor Yoshiaki Nakayama
Yoshiaki Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10867680Abstract: A data erasure device is for a non-volatile semiconductor memory device, which includes cells in which data is written by an application of a first voltage and erased by an application of a second voltage differing from the first voltage. The data erasure device includes a controller. The controller applies a second voltage to the cells over first time period with multiple occurrences to set the cells into a first erasure state, and applies the second voltage to the cells over second time period, which is longer than the first time period, to set the cells in a second erasure state deeper than the first erasure state. The controller changes a number of occurrences of applying the second voltage over the first time period to each of the cells or each of multiple cell groups having the cells according to respective erasure states of the cells.Type: GrantFiled: July 3, 2019Date of Patent: December 15, 2020Assignee: DENSO CORPORATIONInventors: Koichi Yako, Yoshiaki Nakayama
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Patent number: 10761142Abstract: A battery monitoring unit includes a plurality of voltage detection lines, a flexible printed circuit board extending in a stuck direction of single batteries, an electronic circuit connected to one end portions of the plurality of the voltage detection lines so as to detect voltage of each of the single batteries and mounted on the flexible printed circuit board, a plurality of busbar fixing portions formed integrally with the flexible printed circuit board and to which the plurality of the busbars are fixed respectively, and communication lines disposed in the flexible printed circuit board so as to connect between the electronic circuit and a battery ECU.Type: GrantFiled: September 25, 2017Date of Patent: September 1, 2020Assignee: YAZAKI CORPORATIONInventors: Takao Ota, Kazuya Harakawa, Yoshiaki Ichikawa, Yoshiaki Nakayama
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Publication number: 20190325967Abstract: A data erasure device is for a non-volatile semiconductor memory device, which includes cells in which data is written by an application of a first voltage and erased by an application of a second voltage differing from the first voltage. The data erasure device includes a controller. The controller the controller applies a second voltage to the cells over first time period with multiple occurrences to set the cells into a first erasure state, and applies the second voltage to the cells over second time period, which is longer than the first time period, to set the cells in a second erasure state deeper than the first erasure state. The controller changes a number of occurrences of applying the second voltage over the first time period to each of the cells or each of multiple cell groups having the cells according to respective erasure states of the cells.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Inventors: Koichi YAKO, Yoshiaki NAKAYAMA
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Publication number: 20190296149Abstract: In a semiconductor device, a trench is continuously connected to reach a main cell region and a sense cell region, and a shield electrode and a gate electrode layer are continuously connected to reach the main cell region and the sense cell region within the trench. The shield electrode extends to a side of the main cell region away from the sense cell region on one end side of the trench in a longitudinal direction to be electrically connected to an upper electrode. The gate electrode layer extends to a side of the main cell region away from the sense cell region on the other end side of the trench in the longitudinal direction to be electrically connected to a gate liner.Type: ApplicationFiled: June 12, 2019Publication date: September 26, 2019Inventors: Tsuyoshi YAMAMOTO, Kenta GODA, Shunsuke HARADA, Yoshiaki NAKAYAMA
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Patent number: 10424947Abstract: A battery monitoring device includes a battery information input terminal, a battery state monitoring unit, an output terminal, a circuit board, and a housing member. The battery information input terminal is electrically connected to a battery state detecting member. The battery state monitoring unit receives a battery state detection signal via the battery information input terminal. The output terminal outputs monitoring information on the battery state corresponding to the battery state detection signal to an external arithmetic processor. The circuit board is provided with the battery information input terminal, the battery state monitoring unit, and the output terminal. The housing member is integrally formed with the battery information input terminal, the battery state monitoring unit, the output terminal, and the circuit board so as to accommodate at least the whole battery state monitoring unit and the whole circuit board and expose terminal connecting portions to the outside.Type: GrantFiled: January 12, 2018Date of Patent: September 24, 2019Assignee: YAZAKI CORPORATIONInventors: Yuki Chiyajo, Yoshiaki Nakayama, Kimihiro Matsuura, Haruhiko Yoshida
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Publication number: 20180233930Abstract: A battery monitoring device includes a battery information input terminal, a battery state monitoring unit, an output terminal, a circuit board, and a housing member. The battery information input terminal is electrically connected to a battery state detecting member. The battery state monitoring unit receives a battery state detection signal via the battery information input terminal. The output terminal outputs monitoring information on the battery state corresponding to the battery state detection signal to an external arithmetic processor. The circuit board is provided with the battery information input terminal, the battery state monitoring unit, and the output terminal. The housing member is integrally formed with the battery information input terminal, the battery state monitoring unit, the output terminal, and the circuit board so as to accommodate at least the whole battery state monitoring unit and the whole circuit board and expose terminal connecting portions to the outside.Type: ApplicationFiled: January 12, 2018Publication date: August 16, 2018Applicant: Yazaki CorporationInventors: Yuki CHIYAJO, Yoshiaki NAKAYAMA, Kimihiro MATSUURA, Haruhiko YOSHIDA
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Publication number: 20180088179Abstract: A battery monitoring unit includes a plurality of voltage detection lines, a flexible printed circuit board extending in a stuck direction of single batteries, an electronic circuit connected to one end portions of the plurality of the voltage detection lines so as to detect voltage of each of the single batteries and mounted on the flexible printed circuit board, a plurality of busbar fixing portions formed integrally with the flexible printed circuit board and to which the plurality of the busbars are fixed respectively, and communication lines disposed in the flexible printed circuit board so as to connect between the electronic circuit and a battery ECU.Type: ApplicationFiled: September 25, 2017Publication date: March 29, 2018Inventors: Takao Ota, Kazuya Harakawa, Yoshiaki Ichikawa, Yoshiaki Nakayama
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Patent number: 8604513Abstract: A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.Type: GrantFiled: September 23, 2010Date of Patent: December 10, 2013Assignee: DENSO CORPORATIONInventors: Youichi Ashida, Norihito Tokura, Shigeki Takahashi, Yoshiaki Nakayama, Satoshi Shiraki, Kouji Senda
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Publication number: 20110073904Abstract: A semiconductor device includes: a SOI substrate; a semiconductor element having first and second impurity layers disposed in an active layer of the SOI substrate, the second impurity layer surrounding the first impurity layer; and multiple first and second conductive type regions disposed in a part of the active layer adjacent to an embedded insulation film of the SOI substrate. The first and second conductive type regions are alternately arranged. The first and second conductive type regions have a layout, which corresponds to the semiconductor element.Type: ApplicationFiled: September 23, 2010Publication date: March 31, 2011Applicant: DENSO CORPORATIONInventors: Youichi Ashida, Norihito Tokura, Shigeki Takahashi, Yoshiaki Nakayama, Satoshi Shiraki, Kouji Senda
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Patent number: 7799667Abstract: A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.Type: GrantFiled: July 15, 2008Date of Patent: September 21, 2010Assignee: DENSO CORPORATIONInventors: Satoshi Shiraki, Yoshiaki Nakayama, Shoji Mizuno, Takashi Nakano, Akira Yamada
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Publication number: 20090096799Abstract: A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit.Type: ApplicationFiled: December 24, 2008Publication date: April 16, 2009Applicant: Hitachi, Ltd.Inventors: Yoshiaki Nakayama, Nobuaki Kabuto, Yohei Kato
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Publication number: 20090096800Abstract: A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit.Type: ApplicationFiled: December 24, 2008Publication date: April 16, 2009Applicant: Hitachi, Ltd.Inventors: Yoshiaki Nakayama, Nobuaki Kabuto, Yohei Kato
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Publication number: 20080293202Abstract: A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.Type: ApplicationFiled: July 15, 2008Publication date: November 27, 2008Applicant: DENSO CORPORATIONInventors: Satoshi Shiraki, Yoshiaki Nakayama, Shoji Mizuno, Takashi Nakano, Akira Yamada
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Patent number: 7298020Abstract: A wire (12) is formed on an insulating film (10) on a semiconductor substrate (1). The wire (12) is covered by silicon nitride film (14), inorganic SOG film (20) and TEOS film (21). A thin film resistance element (30) of chromium silicon (CrSi) is formed on the upper surface of the TEOS film (21). The acute angle (taper angle) at which a line connecting the local maximum and minimum points of a step on the upper surface of the TEOS film (21) beneath the area where the thin film resistance element (30) is formed intersects to the surface of the substrate (1) is set to 10° or less.Type: GrantFiled: March 11, 2004Date of Patent: November 20, 2007Assignee: DENSO CORPORATIONInventors: Syuji Asano, Yoshiaki Nakayama, Koji Eguchi
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Publication number: 20060086449Abstract: A semiconductor device comprising: an element portion having a heat generation portion; a control circuit portion having a control circuit for controlling the element portion; and a metal member. The element portion and the control circuit portion are adjacently disposed oh a surface portion of a semiconductor substrate. The metal member as an external electrode for the element portion is disposed directly on the element portion through an interlayer insulation film. The metal member is also disposed directly on the control circuit portion through the interlayer insulation film.Type: ApplicationFiled: October 18, 2005Publication date: April 27, 2006Applicant: DENSO CORPORATIONInventor: Yoshiaki Nakayama
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Publication number: 20060071284Abstract: A semiconductor device includes a first insulation film, a second insulation film, a thin film resistor interposed between the insulation films. A predetermined voltage is applied to the thin film resistor so that a current flows through the thin film resistor. When a crack occurs in the insulation films, the thin film resistor is partially destroyed and the resistance of the thin film resistor changes. The crack is detected by measuring the change in resistance of the thin film resistor based on the predetermined voltage and the current flowing through the thin film resistor. Therefore, a crack inspection can be conducted without destruction of the device.Type: ApplicationFiled: September 30, 2005Publication date: April 6, 2006Applicant: DENSO CORPORATIONInventors: Akira Tai, Yoshiaki Nakayama
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Patent number: 6958543Abstract: Semiconductor equipment includes a semiconductor substrate, a plurality of first type semiconductor devices having first and second device regions, a plurality of second type semiconductor devices having the first and second device regions, and upper and lower layer wirings disposed on the substrate. The upper and lower layer wirings electrically connect a plurality of first and second device regions together with a parallel connection, respectively. The lower layer wiring includes a first contact for connecting to the first device region and a second contact for connecting to the second device region. The first contact is concentrated into a predetermined area. The second contact surrounds the first contact. The upper layer wiring disposed on the predetermined area provides a pad area for connecting to an external circuit.Type: GrantFiled: October 14, 2003Date of Patent: October 25, 2005Assignee: Denso CorporationInventor: Yoshiaki Nakayama
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Patent number: 6940144Abstract: Semiconductor equipment includes a semiconductor substrate with a semiconductor layer embedded therein and a vertical type transistor. The substrate has a principal side, a rear side opposite to the principal side, and a trench disposed in the rear side of the substrate. The vertical type transistor has a first electrode disposed in the principal side of the substrate, a second electrode disposed in the rear side, and a diffusion region disposed in the principal side. The first electrode connects to the diffusion region through an interlayer insulation film. The second electrode is disposed in the trench and connects to the semiconductor layer exposed in the trench. This vertical transistor has a low ON-state resistance.Type: GrantFiled: September 16, 2003Date of Patent: September 6, 2005Assignee: Denso CorporationInventor: Yoshiaki Nakayama
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Publication number: 20050141851Abstract: A display apparatus includes a memory circuit for storing information regarding the display apparatus, a read enable unit for allowing an external device to read information from the memory circuit, and a write disable unit for inhibiting a write operation in the memory circuit when either one of the power sources of the display apparatus and the external device turns on, allowing the write operation in the memory circuit in response to a signal from an external terminal used by the read enable unit.Type: ApplicationFiled: August 18, 2004Publication date: June 30, 2005Applicant: Hitachi, Ltd.Inventors: Yoshiaki Nakayama, Nobuaki Kabuto, Yohei Kato
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Publication number: 20050001265Abstract: A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.Type: ApplicationFiled: June 10, 2004Publication date: January 6, 2005Inventors: Satoshi Shiraki, Yoshiaki Nakayama, Shoji Mizuno, Takashi Nakano, Akira Yamada