Patents by Inventor Yoshiaki Nakayama
Yoshiaki Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6831331Abstract: A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.Type: GrantFiled: September 5, 2001Date of Patent: December 14, 2004Assignee: DENSO CorporationInventors: Yasuhiro Kitamura, Toshio Sakakibara, Kenji Kohno, Shoji Mizuno, Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
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Publication number: 20040188770Abstract: A wire (12) is formed on an insulating film (10) on a semiconductor substrate (1). The wire (12) is covered by silicon nitride film (14), inorganic SOG film (20) and TEOS film (21). A thin film resistance element (30) of chromium silicon (CrSi) is formed on the upper surface of the TEOS film (21). The acute angle (taper angle) at which a line connecting the local maximum and minimum points of a step on the upper surface of the TEOS film (21) beneath the area where the thin film resistance element (30) is formed intersects to the surface of the substrate (1) is set to 10° or less.Type: ApplicationFiled: March 11, 2004Publication date: September 30, 2004Applicant: DENSO CORPORATIONInventors: Syuji Asano, Yoshiaki Nakayama, Koji Eguchi
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Publication number: 20040075113Abstract: Semiconductor equipment includes a semiconductor substrate, a plurality of first type semiconductor devices having first and second device regions, a plurality of second type semiconductor devices having the first and second device regions, and upper and lower layer wirings disposed on the substrate. The upper and lower layer wirings electrically connect a plurality of first and second device regions together with a parallel connection, respectively. The lower layer wiring includes a first contact for connecting to the first device region and a second contact for connecting to the second device region. The first contact is concentrated into a predetermined area. The second contact surrounds the first contact. The upper layer wiring disposed on the predetermined area provides a pad area for connecting to an external circuit.Type: ApplicationFiled: October 14, 2003Publication date: April 22, 2004Inventor: Yoshiaki Nakayama
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Publication number: 20040061163Abstract: Semiconductor equipment includes a semiconductor substrate with a semiconductor layer embedded therein and a vertical type transistor. The substrate has a principal side, a rear side opposite to the principal side, and a trench disposed in the rear side of the substrate. The vertical type transistor has a first electrode disposed in the principal side of the substrate, a second electrode disposed in the rear side, and a diffusion region disposed in the principal side. The first electrode connects to the diffusion region through an interlayer insulation film. The second electrode is disposed in the trench and connects to the semiconductor layer exposed in the trench. This vertical transistor has a low ON-state resistance.Type: ApplicationFiled: September 16, 2003Publication date: April 1, 2004Inventor: Yoshiaki Nakayama
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Publication number: 20040021794Abstract: The video display apparatus of the present invention detects a vertical picture size steadily and displays a picture from a video signal accompanied by a closed caption, so that the closed caption does not fall out of the display screen. A closed caption decoder extracts a start line code which determines a position from which a horizontal scan starts along a vertical axis of an active picture area of the video signal and an end line code which determines a position at which the horizontal scan terminates. Based on the start line code and the end line code, a vertical picture size is calculated, and position in which the closed caption information is to be displayed is controlled, according to the vertical picture size.Type: ApplicationFiled: May 19, 2003Publication date: February 5, 2004Inventors: Yoshiaki Nakayama, Katsuya Fujii, Hisaya Fukumoto
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Patent number: 6420281Abstract: One or more capacitors are formed using thermally oxidized films formed on a silicon layer of an SOI substrate. The capacitors may be formed alone or together with other semiconductor elements on a single SOI substrate. A diffuse layer having an impurity in a high density is first formed on the silicon layer, and then an oxidized film is formed on the diffused layer by thermal oxidation. Then, contaminants in the oxidized film are driven-out under a high temperature heat treatment, thereby to improve quality of the oxidized film, such as durability against a high voltage. Plural capacitors may be formed using oxidized films having a respectively different thickness, by repeating thermal oxidation and removal of the oxidized film.Type: GrantFiled: December 6, 2000Date of Patent: July 16, 2002Assignee: Denso CorporationInventors: Takuya Okuno, Akira Yamada, Yoshiaki Nakayama
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Publication number: 20020017697Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: ApplicationFiled: September 5, 2001Publication date: February 14, 2002Applicant: Denso CorporationInventors: Yasuhiro Kitamura, Toshio Sakakibara, Kenji Kohno, Shoji Mizuno, Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
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Patent number: 6336758Abstract: A printer wherein a drive roller of a pair of sheet discharge rollers is made of rubber and a driven roller of the pair of sheet discharge rollers is made of synthetic resin; the leading end of a sheet is guided so as to be abutted against the drive roller earlier than the driven roller; the sheet that is in the course of being discharged is guided by a sheet discharge tray so as to come in slidable contact with an edge portion that is on a print head side of a sheet discharge opening. As a result, the printer can provide satisfactory printing conditions quickly with a simple structure and reduce noise leaking from the sheet discharge opening.Type: GrantFiled: January 19, 1999Date of Patent: January 8, 2002Assignee: Seiko Epson CorporationInventors: Hiroshi Ishida, Shigeki Mizuno, Kenjiro Murakami, Toshikazu Kotaka, Tatsumi Tsuboki, Motoyuki Niimura, Norio Horaguchi, Yoshiaki Nakayama
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Patent number: 6291315Abstract: A semiconductor wafer in which black silicon does not form during trench etching even when side rinsing is carried out during a photolithography process. In an embedded oxide film interposed between first and second semiconductor wafers of a bonded SOI wafer, the film thickness of a peripheral part thereof is made greater than a predetermined thickness Dsio so that it functions as an oxide film for etching prevention. When side rinsing is carried out in a resist coating process to form an opening in an oxide film for masking use in trench etching, the oxide film for masking use at the periphery is also etched during formation of the opening. Due to over-etching at that time, the oxide film for etching prevention is etched by a film thickness d1. During trench etching also, the oxide film for etching prevention is etched by a film thickness d2.Type: GrantFiled: July 10, 1997Date of Patent: September 18, 2001Assignee: Denso CorporationInventors: Yoshiaki Nakayama, Shoji Miura
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Publication number: 20010005605Abstract: One or more capacitors are formed using thermally oxidized films formed on a silicon layer of an SOI substrate. The capacitors may be formed alone or together with other semiconductor elements on a single SOI substrate. A diffused layer having an impurity in a high density is first formed on the silicon layer, and then an oxidized film is formed on the diffused layer by thermal oxidation. Then, contaminants in the oxidized film are driven-out under a high temperature heat treatment, thereby to improve quality of the oxidized film, such as durability against a high voltage. Plural capacitors may be formed using oxidized films having a respectively different thickness, by repeating thermal oxidation and removal of the oxidized film.Type: ApplicationFiled: December 6, 2000Publication date: June 28, 2001Inventors: Takuya Okuno, Akira Yamada, Yoshiaki Nakayama
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Patent number: 6242787Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: GrantFiled: November 15, 1996Date of Patent: June 5, 2001Assignee: Denso CorporationInventors: Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
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Patent number: 6104076Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: GrantFiled: November 15, 1996Date of Patent: August 15, 2000Assignee: Denso CorporationInventors: Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
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Patent number: 5913626Abstract: A printer wherein a drive roller of a pair of sheet discharge rollers is made of rubber and a driven roller of the pair of sheet discharge rollers is made of synthetic resin; the leading end of a sheet is guided so as to be abutted against the drive roller earlier than the driven roller; the sheet that is in the course of being discharged is guided by a sheet discharge tray so as to come in slidable contact with an edge portion that is on a print head side of a sheet discharge opening. As a result, the printer can provide satisfactory printing conditions quickly with a simple structure and reduce noise leaking from the sheet discharge opening.Type: GrantFiled: February 13, 1996Date of Patent: June 22, 1999Assignee: Seiko Epson CorporationInventors: Hiroshi Ishida, Shigeki Mizuno, Kenjiro Murakami, Toshikazu Kotaka, Tatsumi Tsuboki, Motoyuki Niimura, Norio Horaguchi, Yoshiaki Nakayama
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Patent number: 5840234Abstract: A three-dimensional plexifilamentary fiber (26) of a high-density polyethylene group obtained by supplying a polymer to a dissolving area in a state such that the polymer is melted by a heated screw extruder (compressing zone 13, metering zone 14 to 16), supplying a solvent (CCl.sub.3 F) into the melted polymer (feed opening 18), mixing and dissolving the polymer and the solvent to make a polymer solution, and extruding the polymer solution from a nozzle (24 in FIG. 24) arranged in the dissolving area into a low pressure area. A nonwoven fabric is obtained through a process in which the fiber (26) is spread by striking the fiber against a skirt portion (33) having a fiber swinging face (34) and a cushioning face (35), and this nonwoven fabric has an excellent strength, covering property, and whiteness.Type: GrantFiled: March 12, 1996Date of Patent: November 24, 1998Assignee: Asahi Kasei Kogyo Kabushiki KaishaInventors: Kohzoh Ito, Ikuo Ueno, Yoshiaki Nakayama, Katsuzi Hikasa
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Patent number: 5751348Abstract: A movie camera having: a strobe light for illuminating a subject; a shutter speed switching circuit for changing speeds of a shutter for the charge coupled device (CCD); a white balance switching circuit for adjusting the balance between color signals; an automatic gain control (AGC) circuit for adjusting amplifying gain for an image signal; a control circuit for energizing the shutter speed switching circuit so that a flash of the strobe light is terminated within the storing time of the CCD by changing the shutter speed to a higher speed, for energizing the white balance switching circuit so that the white balance is adjusted to coincide with the color temperature of the strobe light, and for fixing the gain of the AGC circuit.Type: GrantFiled: June 6, 1996Date of Patent: May 12, 1998Assignee: Fuji Photo Film Company, Ltd.Inventors: Masafumi Inuiya, Yoshiaki Nakayama
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Patent number: 5711675Abstract: A meter module includes a meter panel in which meters and indication lamps are mounted, a centralized control circuit board in which control circuits for a vehicle's electrical devices (including meters and indication lamps) are installed, an electric junction box for distribution of power, input and output signals and for integration of earth lines, and a module case. The electric junction box is formed by setting a bus-bar circuit board and an insulator cover in the module case. The electric junction box is formed by setting a bus-bar circuit board and an insulator cover in the module case. The centralized control circuit board and the meter panel are fixed over the electric junction box, whereby the meter panel, the centralized control circuit board and the electric junction box are intensively incorporated. Thus, the electric wiring in the instrument panel portion of the vehicle is simplified and this facilitates setting and assembling of the electric devices such as the meter panel.Type: GrantFiled: March 13, 1997Date of Patent: January 27, 1998Assignee: Yasaki CorporationInventors: Keizo Nishitani, Yoshiaki Nakayama, Minoru Kubota, Keiichi Ozaki
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Patent number: 5672894Abstract: The resistance to electromigration in a double-layer Al wiring structure of lateral DMOS or the like is improved by further reducing ON resistance and mitigating current concentration. The first-layer source wiring and the first-layer drain wiring which are electrically connected to a plurality of source cells and drain cells respectively are formed into a pectinate pattern respectively. The second-layer source wiring and the second-layer drain wiring are also formed into a pectinate pattern respectively and disposed in inclination at 45 degrees to the patterns of the first-layer source wiring and first-layer drain wiring.Type: GrantFiled: October 19, 1995Date of Patent: September 30, 1997Assignee: Nippondenso Co., Ltd.Inventors: Hiroshi Maeda, Susumu Ueda, Hiroshi Fujimoto, Yoshiaki Nakayama
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Patent number: 5663866Abstract: An instrument panel with meters/indicating lamps and their drive circuits implemented therein, a centralized control circuit board provided with control circuits for vehicle-mounted electric equipment including the meters/indicating lamps, and an electric junction box for distributing power sources and input/output signals for the vehicle-mounted electric equipment and for integrating ground wires, are gathered and integrally united. Electric wiring and installation of electric instruments such as an instrument panel in the dashboard portion of an automobile are facilitated.Type: GrantFiled: February 15, 1994Date of Patent: September 2, 1997Assignee: Yazaki CorporationInventors: Hiroshi Ichikawa, Yoshiaki Nakayama, Keizo Nishitani, Chiaki Sugiyama, Minoru Kubota, Tatsuo Ikegaya, Masanori Muto, Masaki Oishi, Masahiro Muramatsu, Yasuo Hosoda, Hiroshi Suzuki
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Patent number: 5615080Abstract: A meter module includes a meter panel in which meters and indication lamps are mounted, a centralized control circuit board in which control circuits for car electric devices including the meters and indication lamps are installed, an electric junction box for distribution of power, input and output signals and for integration of earth lines, and a module case. The electric junction box is formed by setting a bus-bar circuit board and an insulator cover in the module case. The centralized control circuit board and the meter panel are fixed over the electric junction box, whereby the meter panel, the centralized control circuit board and the electric junction box are intensively incorporated. The above arrangement simplifies electric wiring in the instrument panel portion of car and facilitates assembling of the electric devices such as the meter panel. A wiring harness protector includes a protector main body for protecting a wiring harness therein and a cover.Type: GrantFiled: March 14, 1994Date of Patent: March 25, 1997Assignee: Yazaki CorporationInventors: Keizo Nishitani, Yoshiaki Nakayama, Minoru Kubota, Keiichi Ozaki
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Patent number: 5607636Abstract: A three-dimensional plexifilamentary fiber (26) of a high-density polyethylene group obtained by supplying a polymer to a dissolving area in a state such that the polymer is melted by a heated screw extruder (compressing zone 13, metering zone 14 to 16), supplying a solvent (CCl.sub.3 F) into the melted polymer (feed opening 18), mixing and dissolving the polymer and the solvent to make a polymer solution, and extruding the polymer solution from a nozzle (24 in FIG. 24 ) arranged in the dissolving area into a low pressure area. A nonwoven fabric is obtained through a process in which the fiber (26) is spread by striking the fiber against a skirt portion (33) having a fiber swinging face (34) and a cushioning face (35), and this nonwoven fabric has an excellent strength, covering property, and whiteness.Type: GrantFiled: April 28, 1994Date of Patent: March 4, 1997Assignee: Asahi Kasei Kogyo Kabushiki KaishaInventors: Kohzoh Ito, Ikuo Ueno, Yoshiaki Nakayama, Katsuzi Hikasa