Patents by Inventor Yoshifumi Kawamoto
Yoshifumi Kawamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5858863Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.Type: GrantFiled: September 27, 1996Date of Patent: January 12, 1999Assignee: Hitachi, Ltd.Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
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Patent number: 5820679Abstract: Disclosed is a fabricating system including a plurality of processing apparatuses connected to each other by means of an inter-apparatus transporter, wherein one group of semiconductor wafers are processed in processing apparatuses and other group of wafers are transported to specified processing apparatuses for a time interval from (To+T) to a time To; and another group of wafers are processed and the remaining group of wafers are transported for a time interval from (To+T) to (To+2T). Since processing apparatuses can receive at least one of works from the inter-apparatus transporter for a time interval T min, the distribution of works from the transporter to processing apparatuses is completed for the time interval T min. The transporter is emptied for each time interval T min, and works are unloaded to the emptied transporter, which makes easy the scheduling, control and management of the transporting of a plurality of works in the fabricating system.Type: GrantFiled: September 12, 1996Date of Patent: October 13, 1998Assignee: Hitachi, Ltd.Inventors: Natsuki Yokoyama, Yoshifumi Kawamoto, Eiichi Murakami, Fumihiko Uchida, Kenichi Mizuishi, Yoshio Kawamura
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Patent number: 5601686Abstract: A wafer transport method including the steps of preparing a semiconductor process equipment having a transport chamber, a process chamber, an interface means for connecting the transport chamber to the process chamber, and a transport means for transporting a semiconductor wafer from the transport chamber to the process chamber by way of the interface means; inserting the transport means mounting a substrate in a communicating corridor including a supply means and an exhaust means; and transporting the substrate while performing the supply and exhaust by sequentially controlling a supply shutoff means, an exhaust shutoff means, and a communicating shutoff means according to the position of a conductance part formed of a gap between the transport means and the communicating corridor.Type: GrantFiled: May 3, 1996Date of Patent: February 11, 1997Assignee: Hitachi, Ltd.Inventors: Yoshio Kawamura, Yoshifumi Kawamoto, Fumihiko Uchida, Kenichi Mizuishi, Natsuki Yokoyama, Eiichi Murakami, Yoshinori Nakayama, Eiichi Seya
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Patent number: 5591998Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: May 17, 1995Date of Patent: January 7, 1997Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5583358Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: October 17, 1994Date of Patent: December 10, 1996Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5562800Abstract: A wafer transport method includes the steps of preparing a semiconductor process equipment having a transport chamber and a process chamber. An interface means connects the transport chamber to the process chamber. A transport means transports a semiconductor wafer from the transport chamber to the process chamber by way of the interface means. The transport means mounting a substrate is inserted into a communicating corridor including a supply means and an exhaust means. The substrate is transported while performing the supply and exhaust by sequentially controlling a supply shutoff means, an exhaust shutoff means, and a communicating shutoff means according to the position of a conductance part formed of a gap between the transport means and the communicating corridor.Type: GrantFiled: September 19, 1994Date of Patent: October 8, 1996Assignee: Hitachi, Ltd.Inventors: Yoshio Kawamura, Yoshifumi Kawamoto, Fumihiko Uchida, Kenichi Mizuishi, Natsuki Yokoyama, Eiichi Murakami, Yoshinori Nakayama, Eiichi Seya
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Patent number: 5426326Abstract: An arrangement is provided to decrease the junction degradation caused by the leakage current at a p-n junction in semiconductor devices. This arrangement can be useful for a variety of devices, and is especially effective for reducing junction degradation at the source or drain region of a MOSFET. To achieve such a reduction, a p-n junction layer is provided at a p-n junction of a semiconductor region and a substrate. Carrier concentration distributions of a p-type layer and an n-type layer of the p-n junction layer are set so that an electric field which tends to be increased by a local electric field enhancement in a depletion layer of the p-n junction due to a precipitate introduced from a semiconductor surface will not exceed 1 MV/cm. When the depth of a depletion layer of the p-type layer or the n-type layer is referred to as Xp or Xn, and the slope of the carrier concentration, Ap or An, the following relation is provided:4.3.times.10.sup.12 (/cm.sup.2).gtoreq.An.multidot.Xn.sup.2 =Ap.multidot.Xp.sup.Type: GrantFiled: August 9, 1993Date of Patent: June 20, 1995Assignee: Hitachi, Ltd.Inventors: Kiyonori Ohyu, Kozo Watanabe, Osamu Tsuchiya, Kazuyoshi Oshima, Yoshifumi Kawamoto, Atsushi Hiraiwa, Takashi Nishida
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Patent number: 5374576Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: June 3, 1993Date of Patent: December 20, 1994Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5357131Abstract: A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.Type: GrantFiled: July 19, 1993Date of Patent: October 18, 1994Assignee: Hitachi, Ltd.Inventors: Hideo Sunami, Tokuo Kure, Yoshifumi Kawamoto, Masao Tamura, Masanobu Miyao
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Patent number: 5237528Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.Type: GrantFiled: January 17, 1992Date of Patent: August 17, 1993Assignee: Hitachi, Ltd.Inventors: Hideo Sunami, Tokuo Kure, Masanobu Miyao, Yoshifumi Kawamoto, Katsuhiro Shimohigashi, Yoshio Sakai, Osamu Minato, Toshiaki Masuhara, Mitsumasa Koyanagi, Shinji Shimizu
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Patent number: 5214496Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.Type: GrantFiled: December 19, 1989Date of Patent: May 25, 1993Assignee: Hitachi, Ltd.Inventors: Hideo Sunami, Tokuo Kure, Masanobu Miyao, Yoshifumi Kawamoto, Katsuhiro Shimohigashi, Yoshio Sakai, Osamu Minato, Toshiaki Masuhara, Mitsumasa Koyanagi, Shinji Shimizu
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Patent number: 5200635Abstract: The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.Type: GrantFiled: April 17, 1991Date of Patent: April 6, 1993Assignee: Hitachi, Ltd.Inventors: Toru Kaga, Shinichiro Kimura, Katsutaka Kimura, Yoshinobu Nakagome, Digh Hisamoto, Yoshifumi Kawamoto, Eiji Takeda, Shimpei Iijima, Tokuo Kure, Takashi Nishida
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Patent number: 5196910Abstract: A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.Type: GrantFiled: February 4, 1991Date of Patent: March 23, 1993Assignee: Hitachi, Ltd.Inventors: Noboru Moriuchi, Yoshiki Yamaguchi, Toshihiko Tanaka, Norio Hasegawa, Yoshifumi Kawamoto, Shin-ichiro Kimura, Toru Kaga, Tokuo Kure
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Patent number: 5140389Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.Type: GrantFiled: February 5, 1990Date of Patent: August 18, 1992Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5118633Abstract: Sources and drains of MOS transistors are formed after the formation of an emitter of a bipolar transistor, whereby the sources and drains are made smaller in thickness than the emitter. Since the sources and drains are not subjected to a high-temperature heat treatment conducted in the formation of the emitter, there is no fear of increase in thickness of the sources and drains caused by the diffusion of impurities. There can be formed a BiCMOS having a high integration density and superior characteristics.Type: GrantFiled: July 25, 1990Date of Patent: June 2, 1992Assignee: Hitachi, Ltd.Inventors: Kazuhiko Sagara, Kiyoo Itoh, Goro Kitsukawa, Yoshifumi Kawamoto, Yoshiki Kawajiri
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Patent number: 5106775Abstract: A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO.sub.2 island is oxidized adjacent its lower end to insulate the island from the substrate.Type: GrantFiled: July 30, 1990Date of Patent: April 21, 1992Assignee: Hitachi, Ltd.Inventors: Toru Kaga, Yoshifumi Kawamoto, Hideo Sunami
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Patent number: 5038193Abstract: In the semiconductor integrated circuit device provided with a plurality of second well regions of the same conductivity type, formed by dividing a first well region provided in the semiconductor substrate by an isolation trench, the isolation trench is substantially linear on the semiconductor substrate surface and the ends reach out of the first well region, however there is no intersection part, namely a corner part T part or cross part in the isolation trench. Therefore, no cavity occurs in the filler in the trench and stress is not concentrated on the intersection part. In addition, defects due to junction leak or mechanical damage do not occur, that is, there is no characteristic deterioration occuring. By providing the second well with memory cell, a semiconductor memory device whose characteristic defect rate and reliability defect rate are remarkably low can be formed.Type: GrantFiled: June 21, 1990Date of Patent: August 6, 1991Assignees: Hitachi VLSI, Hitachi, Ltd. & Engineering Corp.Inventors: Yoshiaki Kamigaki, Shinichi Minami, Kazunori Furusawa, Yoshifumi Kawamoto, Shoji Shukuri, Masaaki Terasawa, Yasunori Ikeda, Hidefumi Mukohda
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Patent number: 5017981Abstract: A semiconductor memory is provided having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor. In particular, an arrangement is provided to prevent a depletion region formed around the groove from growing into an adjacent capacitor. By virtue of this, both the area occupied by each memory cell and the distance between the memory cells can be made very small. Accordingly, high density integration is facilitated.Type: GrantFiled: June 10, 1988Date of Patent: May 21, 1991Assignee: Hitachi, Ltd.Inventors: Hideo Sunami, Tokuo Kure, Yoshifumi Kawamoto
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Patent number: 5012310Abstract: A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.Type: GrantFiled: August 13, 1990Date of Patent: April 30, 1991Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Yoshifumi Kawamoto, Toru Kaga, Hideo Sunami
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Patent number: 5012312Abstract: The impurity concentration in a channel stopper in contact with a second fine active area is selected to be lower than the impurity concentration in a first active area that is wider than the second active area. This prevents the impurity concentration in the second active area from excessively rising that is caused by the diffusion of impurities when the insulating film for isolation is being formed, and helps improve characteristics and reliability of fine semiconductor device formed in the second active area.Type: GrantFiled: October 25, 1988Date of Patent: April 30, 1991Assignee: Hitachi, Ltd.Inventor: Yoshifumi Kawamoto