Patents by Inventor Yoshifumi Kawamoto

Yoshifumi Kawamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4984030
    Abstract: A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.
    Type: Grant
    Filed: May 31, 1988
    Date of Patent: January 8, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Tokuo Kure, Yoshifumi Kawamoto, Masao Tamura, Masanobu Miyao
  • Patent number: 4970564
    Abstract: A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.
    Type: Grant
    Filed: December 21, 1988
    Date of Patent: November 13, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto
  • Patent number: 4967247
    Abstract: A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO.sub.2 island is oxidized adjacent its lower end to insulate the island from the substrate.
    Type: Grant
    Filed: December 2, 1988
    Date of Patent: October 30, 1990
    Assignee: Hitachi, Ltd
    Inventors: Toru Kaga, Yoshifumi Kawamoto, Hideo Sunami
  • Patent number: 4901128
    Abstract: A semiconductor memory comprises a capacitor with a data storage portion, and an insulated-gate field-effect transistor. The capacitor is formed by a plate which is made up of the side walls and base of a groove formed in a semiconductor substrate, and by a capacitor electrode formed on the side walls and the base, over an insulation film, and which is connected electrically to the source or drain of the insulated-gate field-effect transistor. Various embodiments are provided for reducing size and preventing leakage between other memory cells, including forming stacked capacitors, forming the transistor over the capacitor, using a silicon-over-insulator arrangement for the transistor, forming a common capacitor plate and providing high impurity layers within the substrate.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: February 13, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Tokuo Kure, Masanobu Miyao, Yoshifumi Kawamoto, Katsuhiro Shimohigashi, Yoshio Sakai, Osamu Minato, Toshiaki Masuhara, Mitsumasa Koyanagi, Shinji Shimizu
  • Patent number: 4882289
    Abstract: A semiconductor memory wherein a memory cell region having a plurality of memory cells and has higher altitude from the surface of semiconductor substrate is formed in the recessed part of semiconductor substrate having the recessed part and projected part and a peripheral circuit region which is comparatively low from the surface of semiconductor substrate is formed to the projected part of semiconductor substrate.
    Type: Grant
    Filed: April 22, 1988
    Date of Patent: November 21, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Moriuchi, Yoshiki Yamaguchi, Toshihiko Tanaka, Norio Hasegawa, Yoshifumi Kawamoto, Shin-ichiro Kimura, Toru Kaga, Tokuo Kure
  • Patent number: 4873203
    Abstract: An insulation film on silicon buried in a trench is prepared by forming a field oxide film by using a first Si.sub.3 N.sub.4 mask formed on a silicon substrate, forming a second Si.sub.3 N.sub.4 mask for formation of a trench, forming a trench in the silicon substrate by using the second Si.sub.3 N.sub.4 mask, burying polycrystalline silicon in the trench, removing the second Si.sub.3 N.sub.4 mask while leaving the first Si.sub.3 N.sub.4 mask and oxidizing the surface of the polycrystalline silicon buried in the trench by thermal oxidation. The so-formed insulation film on silicon buried in the trench has a uniform thickness and a high dielectric strength. The surface of the substrate at a part where an active element will be formed in the future is not oxidized.
    Type: Grant
    Filed: July 19, 1988
    Date of Patent: October 10, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Toru Kaga, Shinichiro Kimura, Tokuo Kure, Yoshifumi Kawamoto, Hideo Sunami
  • Patent number: 4853894
    Abstract: A semiconductor memory having static cells each composed of two driver MOS transistors formed on a semiconductor substrate and two transfer MOS transistors and two load resistors, which are formed on the substrate and are connected to the drains of the driver MOS transistors, respectively. A conductive film for fixing the sources of the driver MOS transistors to a ground voltage is formed above the principal surface of the semiconductor substrate, and this conductive film defines one electrode of a capacitance element formed on the substrate. The conductive film is formed over the load resistors formed on the semiconductor substrate so as to constitute an electric field shield for the load resistors.
    Type: Grant
    Filed: July 9, 1987
    Date of Patent: August 1, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Toshiaki Yamanaka, Norio Suzuki, Yoshio Sakai, Yoshifumi Kawamoto, Osamu Minato, Koichiro Ishibashi, Nobuyuki Moriwaki, Satoshi Meguro
  • Patent number: 4751557
    Abstract: A semiconductor memory wherein a part of each capacitor is formed on side walls of an island region surrounded with a recess formed in a semiconductor substrate, and the island region and other regions are electrically isolated by the recess.
    Type: Grant
    Filed: September 8, 1986
    Date of Patent: June 14, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Tokuo Kure, Yoshifumi Kawamoto, Masao Tamura, Masanobu Miyao
  • Patent number: 4529476
    Abstract: A dry-etching gas suitable for selective etching of silicon nitride and a process for selectively dry-etching silicon nitride with the dry-etching gas are disclosed. Silicon nitride can be dry-etched with a higher selectivity or at a higher etching rate than silicon dioxide and silicon, and a process for fabricating semi-conductor devices can be simplified and devices with a novel structure can be realized.
    Type: Grant
    Filed: June 1, 1984
    Date of Patent: July 16, 1985
    Assignees: Showa Denko K.K., Hitachi, Ltd.
    Inventors: Yoshifumi Kawamoto, Hiroshi Kawakami, Tokuo Kure, Shinichi Tachi, Norikazu Hashimoto, Tsuyoshi Takaichi