Patents by Inventor Yoshifumi Nishi

Yoshifumi Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220269932
    Abstract: A synaptic circuit according to an embodiment is a circuit in which a weight value changed by learning is set. The synaptic circuit receives a binary input signal from a pre-synaptic neuron circuit and outputs an output signal to a post-synaptic neuron circuit. The synaptic circuit includes a propagation circuit and a control circuit. The propagation circuit supplies, to the post-synaptic neuron circuit, the output signal obtained by adding an influence of the weight value to the input signal. The control circuit stops output of the output signal from the propagation circuit to the post-synaptic neuron circuit when the weight value is smaller than a predetermined reference value.
    Type: Application
    Filed: August 30, 2021
    Publication date: August 25, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumiko NOMURA, Yoshifumi Nishi, Takao Marukame, Koichi Mizushima
  • Publication number: 20220271135
    Abstract: In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between. the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film. is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating. film and the second electrode film.
    Type: Application
    Filed: August 30, 2021
    Publication date: August 25, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi MIZUSHIMA, Takao MARUKAME, Yoshifumi NISHI, Kumiko NOMURA
  • Publication number: 20220237452
    Abstract: A neural network device according to an embodiment includes an arithmetic circuit, a learning control circuit, and a bias reset circuit. The arithmetic circuit executes arithmetic processing according to a neural network using a plurality of weights each represented by a value of a first resolution and a plurality of biases each represented by a value in ternary. At the time of learning of the neural network, the learning control circuit repeats a learning process of updating each of the plurality of weights and each of the plurality of biases a plurality of times based on a result of the arithmetic processing according to the neural network performed by the arithmetic circuit. In each learning process, the bias reset circuit resets a bias randomly selected with a preset first probability among the plurality of biases to a median in the ternary.
    Type: Application
    Filed: August 26, 2021
    Publication date: July 28, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Koichi MIZUSHIMA, Kumiko NOMURA, Yoshifumi NISHI
  • Publication number: 20220215229
    Abstract: According to one embodiment, there is provided a neural network device including a neuron, a conversion part, a transmission part, a control part and a holding part. The conversion part converts a spike signal to a synapse current according to weight. The transmission part transmits the converted synapse current to the neuron. The control part determines transition of a state of the weight. The holding part holds the weight as a discrete state according to the determined transition of the state. The holding part includes an action part that stochastically operates based on a signal input from the control part to cause transition of the state of the weight. A cumulative probability of actions of the action part changes in a sigmoidal shape with respect to number of signal input times.
    Type: Application
    Filed: August 30, 2021
    Publication date: July 7, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi NISHI, Kumiko NOMURA, Takao MARUKAME, Koichi MIZUSHIMA
  • Patent number: 11380375
    Abstract: A storage device according to an embodiment is for storing weights being continuous values. The storage device includes: a shift register, an initialization circuit, an update control circuit, and a readout control circuit. The shift resistor includes a plurality of cells, each being arranged in series and storing information. A position of each of the plurality of cells corresponds to the weight. The initialization circuit writes the information to a cell in the shift register. The update control circuit shifts a position of the cell storing the information in a direction corresponding to a sign of an update amount by a number of cells corresponding to an absolute value of the update amount. The readout control circuit reads out the information and outputs an output value according to the weight corresponding to the position of the cell storing the information.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 5, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Koichi Mizushima, Kumiko Nomura, Yoshifumi Nishi
  • Publication number: 20220197352
    Abstract: Magnetically actuated doors are disclosed. A disclosed example apparatus includes a door to be movably coupled to a frame of a computing device, a first magnet, a magnet array including a second magnet and a third magnet, the door to support the first magnet or the magnet array, and a slide. The slide includes a body supporting the other of the first magnet or the magnet array, and a guide, the body to move along a path defined by the guide, wherein the body in a first location of the path causes the magnet array to attract the first magnet and close the door relative to the frame, and wherein the body in a second location of the path causes the magnet array to repel the first magnet and open the door relative to the frame.
    Type: Application
    Filed: March 11, 2022
    Publication date: June 23, 2022
    Inventors: Yoshifumi Nishi, Alex Gilpin
  • Publication number: 20220126835
    Abstract: Embodiments include apparatuses, methods, and systems for computer assisted or autonomous driving (CA/AD). An apparatus for CA/AD may include a sensor interface, a communication interface, and a driving strategy unit. The sensor interface may receive sensor data indicative of friction between a road surface of a current location of a CA/AD vehicle and one or more surfaces of one or more tires of the CA/AD vehicle. The communication interface may receive, from an external road surface condition data source, data indicative of friction for a surface of a road section ahead of the current location of the CA/AD vehicle. The driving strategy unit may determine, based at least in part on the sensor data and the data received from the external road surface condition data source, a driving strategy for the CA/AD vehicle beyond the current location of the CA/AD vehicle. Other embodiments may also be described and claimed.
    Type: Application
    Filed: January 6, 2022
    Publication date: April 28, 2022
    Inventors: Yoshifumi Nishi, David Pidwerbecki, David Browning, Mark Angus MacDonald
  • Publication number: 20220083845
    Abstract: An arithmetic device includes N product-sum-operation circuits, a control circuit, and an output circuit. Each product-sum-operation circuit outputs intermediate signals obtained by binarizing a product-sum-operation value obtained by product-sum-operation of M input values of M input signals and M weight values. The control circuit inverts positive/negative of each M weight value at determining-timing when a given time elapses from input timing. Based on a delay time from the determination-timing to logic finalization of the intermediate signal for each N product-sum-operation circuit, the output circuit outputs an output signal representing a winner-product-sum-operation circuit for which the product-sum-operation value having a sign and the largest absolute value is calculated.
    Type: Application
    Filed: February 24, 2021
    Publication date: March 17, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Koichi MIZUSHIMA, Kumiko NOMURA, Yoshifumi NISHI
  • Patent number: 11267475
    Abstract: Embodiments include apparatuses, methods, and systems for computer assisted or autonomous driving (CA/AD). An apparatus for CA/AD may include a sensor interface, a communication interface, and a driving strategy unit. The sensor interface may receive sensor data indicative of friction between a road surface of a current location of a CA/AD vehicle and one or more surfaces of one or more tires of the CA/AD vehicle. The communication interface may receive, from an external road surface condition data source, data indicative of friction for a surface of a road section ahead of the current location of the CA/AD vehicle. The driving strategy unit may determine, based at least in part on the sensor data and the data received from the external road surface condition data source, a driving strategy for the CA/AD vehicle beyond the current location of the CA/AD vehicle. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: March 8, 2022
    Assignee: Intel Corporation
    Inventors: Yoshifumi Nishi, David Pidwerbecki, David Browning, Mark Angus MacDonald
  • Publication number: 20220068326
    Abstract: A storage device according to an embodiment is for storing weights being continuous values. The storage device includes: a shift register, an initialization circuit, an update control circuit, and a readout control circuit. The shift resistor includes a plurality of cells, each being arranged in series and storing information. A position of each of the plurality of cells corresponds to the weight. The initialization circuit writes the information to a cell in the shift register. The update control circuit shifts a position of the cell storing the information in a direction corresponding to a sign of an update amount by a number of cells corresponding to an absolute value of the update amount. The readout control circuit reads out the information and outputs an output value according to the weight corresponding to the position of the cell storing the information.
    Type: Application
    Filed: February 25, 2021
    Publication date: March 3, 2022
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Koichi MIZUSHIMA, Kumiko NOMURA, Yoshifumi NISHI
  • Patent number: 11150873
    Abstract: An arithmetic apparatus according to an embodiment outputs a multiplicative value obtained by multiplying a weight value and an input value. The arithmetic apparatus includes a memristor, a logarithmic transform circuit, and a current-voltage converter circuit. The memristor is a device capable of changing voltage-current characteristic, and the memristor is preset to voltage-current characteristic according to the weight value. The logarithmic transform circuit applies an intermediate voltage, to the memristor, that is obtained by logarithmically transforming an input voltage according to the input value in accordance with a logarithmic transform function obtained by multiplying a natural logarithm function by a preset coefficient. The current-voltage converter circuit outputs an output voltage obtained by performing current-voltage conversion of current flowing through the memristor according to a preset linear function, as a multiplicative value.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: October 19, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Radu Berdan, Yoshifumi Nishi, Takao Marukame
  • Patent number: 11132857
    Abstract: Various systems and methods for providing a smart entry system are described herein. A smart entry system includes a detector to detect a person near a portal to a room; a transceiver to attempt to establish a wireless connection between the smart entry system and a user device associated with the person; and a user interface to present a notification to the person based on a state of the wireless connection.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: David W. Browning, Mark MacDonald, Yoshifumi Nishi
  • Publication number: 20210279558
    Abstract: A synaptic circuit according to an embodiment includes: a weight current circuit that applies a weight current corresponding to a weight value; an input switch that switches whether or not to cause the weight current circuit to apply the weight current; a capacitor that includes a first terminal and a second terminal, the first terminal being given a constant voltage; an output circuit that outputs the output signal corresponding to a capacitor voltage; a charge adjustment circuit that decreases or increases charges accumulated in the capacitor by drawing, from the second terminal, a capacitor current corresponding to a current value of the weight current, or supplying the capacitor current to the second terminal; and a control circuit that switches whether or not to reduce a current having a predetermined current value from the capacitor current in accordance with the weight value.
    Type: Application
    Filed: August 28, 2020
    Publication date: September 9, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kumiko NOMURA, Takao MARUKAME, Yoshifumi NISHI, Koichi MIZUSHIMA
  • Publication number: 20210279559
    Abstract: A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a determinator, a synaptic depressor, and a synaptic potentiator. The synaptic element has a variable weight and outputs, in response to input of a first spike signal, a synaptic signal having intensity adjusted in accordance with the weight. The neuron circuit outputs a second spike signal in a case where the synaptic signal is inputted and a predetermined firing condition for the synaptic signal is satisfied. The determinator determines whether or not the weight is to be updated on a basis of an output frequency of the second spike signal by the neuron circuit. The synaptic depressor performs depression operation for depressing the weight in a case where it is determined that the weight is to be updated. The synaptic potentiator performs potentiating operation for potentiating the weight.
    Type: Application
    Filed: August 31, 2020
    Publication date: September 9, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi NISHI, Kumiko NOMURA, Takao MARUKAME, Koichi MIZUSHIMA
  • Publication number: 20210216282
    Abstract: According to an embodiment, an arithmetic device includes a comparator, M cross switches, and M coefficient circuits. The comparator compares a first voltage generated at a first comparison terminal and a second voltage generated at a second comparison terminal. The M cross switches are provided corresponding to the M input signals. The M coefficient circuits are provided corresponding to the M coefficients, and each includes a first constant current source and a second constant current source. Each of the M cross switches performs switching between a straight state and a reverse state. In each of the M coefficient circuits, the first constant current source is connected between a positive output terminal of the corresponding coefficient circuit and a reference potential, and the second constant current source is connected between a negative output terminal of the corresponding coefficient circuit and the reference potential.
    Type: Application
    Filed: August 27, 2020
    Publication date: July 15, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Koichi MIZUSHIMA, Kumiko NOMURA, Yoshifumi NISHI
  • Patent number: 11059375
    Abstract: Robots and apparatus, systems and methods for powering robots are disclosed. A disclosed conductive floor to power a robot on the floor includes a plurality of stationary conductors positioned in a pattern and a power delivery circuit to cause adjacent ones of the conductors to have different electrical potentials, the adjacent ones of the conductors to form a circuit to deliver power to the robot via contacts formed in a bottom surface of the robot.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: July 13, 2021
    Assignee: INTEL CORPORATION
    Inventors: David W. Browning, Yoshifumi Nishi, Mark MacDonald
  • Publication number: 20210081771
    Abstract: According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.
    Type: Application
    Filed: February 26, 2020
    Publication date: March 18, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao MARUKAME, Kumiko NOMURA, Yoshifumi NISHI, Koichi MIZUSHIMA
  • Patent number: 10942705
    Abstract: According to an embodiment, a quantum annealing apparatus includes: an output unit acquiring and outputting components in a Z axis from a plurality of quantum bits in a quantum calculation; and an operation unit executes: a selecting process of selecting a first quantum bit, a second quantum bit and a third quantum bit, the second quantum bit and the third quantum bit being coupled in the quantum calculation unit; a first rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a first axis perpendicular to the Z axis; an interaction operation of causing the first quantum bit and the second quantum bit to interact with each other; and a second rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a second axis perpendicular to the Z axis and the first axis.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: March 9, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventors: Tetsufumi Tanamoto, Yoshifumi Nishi, Jun Deguchi
  • Publication number: 20210056383
    Abstract: A spiking neural network device according to an embodiment includes a synaptic element, a neuron circuit, a synaptic potentiator, and a synaptic depressor. The synaptic element has a variable weight. The neuron circuit inputs a spike voltage having a magnitude adjusted in accordance with the weight of the synaptic element via the synaptic element, and fires when a predetermined condition is satisfied. The synaptic potentiator performs a potentiating operation for potentiating the weight of the synaptic element depending on input timing of the spike voltage and firing timing of the neuron circuit. The synaptic depressor performs a depression operation for depressing the weight of the synaptic element in accordance with a schedule independent from the input timing of the spike voltage and the firing timing of the neuron circuit.
    Type: Application
    Filed: February 27, 2020
    Publication date: February 25, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshifumi NISHI, Kumiko NOMURA, Radu BERDAN, Takao MARUKAME
  • Patent number: 10891108
    Abstract: A calculation device includes: M coefficient storage units provided corresponding to the M coefficients, each of the M coefficient storage units including a positive-side coefficient and a negative-side coefficient representing a coefficient corresponding to a sign of a difference; M multiplication units provided corresponding to the M input values, each of the M multiplication units calculating a positive-side multiply value obtained by multiplying the positive-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value and a negative-side multiply value obtained by multiplying the negative-side coefficient included in the corresponding coefficient storage unit by a sign inverted according to the corresponding input value; and an output unit outputting an value according to a difference between a positive-side sum value obtained by summing the M positive-side multiplication values and a negative-side sum value obtained by summing the M
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 12, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takao Marukame, Yoshifumi Nishi, Kumiko Nomura