Patents by Inventor Yoshifumi Nishi

Yoshifumi Nishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9769966
    Abstract: Methods and apparatus relating to EMI (Electromagnetic Interference) shielding structure to enable heat spreading and/or low cost assembly are described. In an embodiment, a metallic shield at least partially surrounds at least one logic component. The metallic shield includes a dome feature to provide thermal contact between the at least one logic component and the metallic shield. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventor: Yoshifumi Nishi
  • Publication number: 20170258371
    Abstract: Low-cost, easy-to-use alignment target generators for aligning a user's own face or eye to a camera or scanner are based on field-of-view visual feedback from a filtered or apertured planar light source. These approaches may be made agnostic to the scanner's operating system or other software. Alternatively, software on the scanner or its host device may create a solid light-colored section of an existing display screen to use as a planar light source. In some embodiments, the planar light source may be the virtual image of an object viewed in a plane mirror.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Kerry A. Stevens, Yoshifumi Nishi
  • Patent number: 9672103
    Abstract: According to an embodiment, a decoding device includes a check node processor, and a converter. The probability acquirer is configured to acquire. The check node processor is configured to perform check node processing during in a decoding operation of encoded data. A probability value for each bit of the encoded data is treated as an initial variable node in the check node processing. The converter is configured to convert, into bit values, updated values of the probability values based on the check node processing. The check node processor includes a check node circuit having a topology corresponding to a two-state trellis diagram representing the check node processing. The check node circuit includes conducting wires each corresponding to an edge of the two-state trellis diagram and includes switch units which are arranged on the conducting wires and switching of which is controlled according to a predetermined probability.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshifumi Nishi, Takao Marukame, Yuichiro Mitani
  • Publication number: 20170094844
    Abstract: Methods and apparatus relating to EMI (Electromagnetic Interference) shielding structure to enable heat spreading and/or low cost assembly are described. In an embodiment, a metallic shield at least partially surrounds at least one logic component. The metallic shield includes a dome feature to provide thermal contact between the at least one logic component and the metallic shield. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Applicant: Intel Corporation
    Inventor: Yoshifumi Nishi
  • Publication number: 20170075422
    Abstract: A wearable device (e.g., a headset (100)) for the human ear (202) and having an infrared (IR) temperature sensor (102) to facilitate control of a media device (700) coupled to the wearable device. The control may be based at least in part on the measured temperature indicated by the IR sensor (102) detecting the wearable device as on (or off) an ear of a user.
    Type: Application
    Filed: June 9, 2014
    Publication date: March 16, 2017
    Applicant: Intel Corporation
    Inventors: Yanbing Sun, Jian Wang, Mark MacDonald, Yoshifumi Nishi
  • Patent number: 9570181
    Abstract: According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Kazuya Matsuzawa, Yoshifumi Nishi, Jiezhi Chen, Yusuke Higashi, Yuuichiro Mitani
  • Patent number: 9551352
    Abstract: Embodiments of an apparatus, system, method and techniques are described for an improved volumetric resistance blower and rotor. An apparatus may comprise, for example a motor, a casing having one or more inlets and one or more outlets, and a cylindrical rotor to create a volumetric resistance inside the casing, at least a portion of the rotor comprising a porous material. Other embodiments are described.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: January 24, 2017
    Assignee: INTEL CORPORATION
    Inventors: Mark MacDonald, Douglas Heymann, Jered H. Wikander, Yoshifumi Nishi
  • Publication number: 20160374550
    Abstract: Low-cost, easy-to-use alignment target generators for aligning a user's own face or eye to a camera or scanner are based on field-of-view visual feedback from a filtered or apertured planar light source. These approaches may be made agnostic to the scanner's operating system or other software. Alternatively, software on the scanner or its host device may create a solid light-colored section of an existing display screen to use as a planar light source. In some embodiments, the planar light source may be the virtual image of an object viewed in a plane mirror.
    Type: Application
    Filed: June 27, 2015
    Publication date: December 29, 2016
    Inventors: Kerry A. Stevens, Yoshifumi Nishi
  • Patent number: 9472756
    Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a variable resistance layer. The variable resistance layer is provided between the first electrode and the second electrode. The variable resistance layer contains impurity of a nonmetallic element. The impurity is at least one selected from the group consisting of S, Se, Te, F, Cl, Br, and I.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 18, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ishikawa, Yoshifumi Nishi, Shosuke Fujii
  • Publication number: 20160226523
    Abstract: According to an embodiment, a decoding device includes a variable node processor, a check node processor, a first forwarder, and a second forwarder. The variable node processor is configured to perform variable node processing on variable nodes defined by a code and output first messages. The check node processor is configured to perform check node processing on check nodes defined by the code based on the first messages and output second messages. The first forwarder is configured to forward one or more first messages remaining after excluding messages to be forwarded to one or more check nodes corresponding to one or more of the second messages having been stored in ae storage, to the check nodes. The second forwarder is configured to forward the second messages to the variable nodes and forward the one or more of the second messages to the storage.
    Type: Application
    Filed: October 27, 2015
    Publication date: August 4, 2016
    Inventors: Yoshifumi NISHI, Takao MARUKAME, Yuichiro MITANI
  • Publication number: 20160187927
    Abstract: Methods and apparatus relating for direct attach dock cooling leveraging Maximum Silicon Junction Temperature (Tj) control are described. In an embodiment, performance of a mobile computing device is increased based at least in part on an indication that the mobile computing device is coupled to a dock. The dock includes a cooling fan proximate to a hotspot on a back skin of the mobile computing device. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Applicant: Intel Corporation
    Inventors: MARK A. MACDONALD, YOSHIFUMI NISHI
  • Publication number: 20160180938
    Abstract: According to an embodiment, a memory system includes first wiring lines; second wiring lines; third wiring lines; fourth wiring lines; and first and second storages. The first storage includes first memory cells arranged at intersections of the first wiring lines and the second wiring lines. Each of the third wiring lines is connected to any one of the first wiring lines. Each of the fourth wiring lines is pre-associated with a logical address specified by a host apparatus. The second storage includes second memory cells arranged at intersections of the third wiring lines and the fourth wiring lines. A resistance state of each of the second memory cells is set to a first resistance state or a second resistance state where a resistance value is lower than that in the first resistance state, according to a correspondence relationship between the logical address and the first wiring line.
    Type: Application
    Filed: March 2, 2016
    Publication date: June 23, 2016
    Inventors: Takao MARUKAME, Kazuya MATSUZAWA, Yoshifumi NISHI, Jiezhi CHEN, Yusuke HIGASHI, Yuuichiro MITANI
  • Publication number: 20160149834
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Application
    Filed: December 18, 2015
    Publication date: May 26, 2016
    Inventors: Kosuke TATSUMURA, Atsuhiro KINOSHITA, Hirotaka NISHINO, Masamichi SUZUKI, Yoshifumi NISHI, Takao MARUKAME, Takahiro KURITA
  • Publication number: 20160085626
    Abstract: According to an embodiment, a decoding device includes a check node processor, and a converter. The probability acquirer is configured to acquire. The check node processor is configured to perform check node processing during in a decoding operation of encoded data. A probability value for each bit of the encoded data is treated as an initial variable node in the check node processing. The converter is configured to convert, into bit values, updated values of the probability values based on the check node processing. The check node processor includes a check node circuit having a topology corresponding to a two-state trellis diagram representing the check node processing. The check node circuit includes conducting wires each corresponding to an edge of the two-state trellis diagram and includes switch units which are arranged on the conducting wires and switching of which is controlled according to a predetermined probability.
    Type: Application
    Filed: September 8, 2015
    Publication date: March 24, 2016
    Inventors: Yoshifumi NISHI, Takao MARUKAME, Yuichiro MITANI
  • Publication number: 20160085627
    Abstract: According to an embodiment, a memory system includes a memory and a computation unit. Into the memory, data are written. The memory stores therein multiple check matrices. Each of the check matrices is associated with the number of errors in the written data. The computation unit is configured to perform a first error correction on the written data by selectively using, from among the check matrices, a check matrix associated with the number of errors recognized in the written data.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 24, 2016
    Inventors: Takao MARUKAME, Yoshifumi NISHI, Yusuke HIGASHI, Jiezhi CHEN, Kazuya MATSUZAWA, Yuichiro MITANI
  • Patent number: 9246709
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: January 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Patent number: 9210991
    Abstract: An apparatus and method for keeping mobile devices warm in cold climates are disclosed. A particular embodiment includes: a frame structure wherein a first portion of the frame structure being in proximity to the body of a user to receive body heat from the user, the frame structure including a second portion to support electronic components of the apparatus; and a thermal conduit thermally coupled between the first and second portions of the frame structure, the thermal conduit transferring body heat received at the first portion to the electronic components of the apparatus at the second portion.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: December 15, 2015
    Assignee: Intel Corporation
    Inventors: Yoshifumi Nishi, Douglas Heymann
  • Patent number: 9152350
    Abstract: According to an embodiment, a semiconductor memory device includes a controller and a second storage unit. The controller is configured to control a write process of writing data into a first storage unit in which data supplied from a host device are stored or a read process of reading the data stored in the first storage in response to a request from the host device. The second storage unit is temporarily used in the write process or the read process. The second storage unit includes a nonvolatile third storage unit having an area for storing a duplicate of the data to be written by the write process; and a nonvolatile fourth storage unit having a work area for the write process or the read process and having a higher read/write speed than the third storage unit.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: October 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Marukame, Atsuhiro Kinoshita, Takahiro Kurita, Yoshifumi Nishi
  • Publication number: 20150263117
    Abstract: A semiconductor device according to an embodiment comprises: a gate insulating film formed on a semiconductor substrate; a semiconductor layer formed on the gate insulating film; and a first metal layer formed to be electrically connected to the semiconductor layer. 1×1019 atoms/cm3 or more of a Group VI element exists in an interface of the semiconductor layer and the first metal layer.
    Type: Application
    Filed: September 12, 2014
    Publication date: September 17, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi KATO, Takao MARUKAME, Yoshifumi NISHI, Yuichiro MITANI, Takahisa KANEMURA, Kazuya OHUCHI
  • Patent number: 9134757
    Abstract: An electronic device is provided that includes a base having a first side and a second side, and a lid having a first side and a second side. The electronic device may also include a heat exchanger provided at the base. The heat exchanger may have a first surface exposed to outside the base.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 15, 2015
    Assignee: Intel Corporation
    Inventors: Yoshifumi Nishi, Mark MacDonald, Douglas Heymann