Abstract: An apparatus and method for keeping mobile devices warm in cold climates are disclosed. A particular embodiment includes: a frame structure wherein a first portion of the frame structure being in proximity to the body of a user to receive body heat from the user, the frame structure including a second portion to support electronic components of the apparatus; and a thermal conduit thermally coupled between the first and second portions of the frame structure, the thermal conduit transferring body heat received at the first portion to the electronic components of the apparatus at the second portion.

Abstract: A memory device includes a first electrode, a second electrode, a third electrode, a first variable resistance layer between the first electrode and the third electrode, and a second variable resistance layer between the second electrode and the third electrode. The first, second, and third electrodes, and the first and second variable resistance layers are formed of materials that cause the first variable resistance layer to transition from a high resistance state to a low resistance state when a voltage is applied across the first and second electrodes and maintain the high resistance state when the voltage is cut off, and cause the second variable resistance layer to transition from a high resistance state to a low resistance state when the voltage is applied across the first and second electrodes and transition from the high resistance state to the low resistance state when the voltage is cut off.

Abstract: In one embodiment a heat exchanger assembly comprises at least one heat pipe and a casing which is to receive a blower, the casing comprising a plurality of heat exchanging plates, wherein at least one of the heat exchanging plates comprises at least one tongue which is to cover a portion of an exterior surface of the at least one heat pipe. Other embodiments may be described.

Abstract: According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1. Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.

Abstract: A semiconductor device according to an embodiment includes: a first transistor including a gate connected to a first interconnection, a first source, and a first drain, one of the first source and the first drain being connected to a second interconnection; and a second transistor including a gate structure, a second source, and a second drain, one of the second source and second drain being connected to a third interconnection and the other of the second source and second drain being connected to a fourth interconnection. The gate structure includes a gate insulation film, a gate electrode, and a threshold-modulating film provided between the gate insulation film and the gate electrode to modulate a threshold voltage, the other of the first source and first drain of the first transistor is connected to the gate electrode.

Abstract: An electronic device is provided that includes a base having a top portion and a bottom portion. The bottom portion may include a first bottom part and a second bottom part. The first bottom part may form a first plane, and the second bottom part may form a second plane, the second plane being non-planar with the first plane. The second bottom part may include an input opening. The top portion of the base may include an output opening. The input opening and the output opening may allow air to flow from behind the electronic device to over the base.

Abstract: Embodiments of an apparatus, system, method and techniques are described for an improved volumetric resistance blower and rotor. An apparatus may comprise, for example a motor, a casing having one or more inlets and one or more outlets, and a cylindrical rotor to create a volumetric resistance inside the casing, at least a portion of the rotor comprising a porous material. Other embodiments are described.

Abstract: A semiconductor device including a semiconductor substrate, an interface layer formed on the semiconductor substrate including at least 1×1020 atoms/cm3 of S (Sulfur), a metal-semiconductor compound layer formed on the interface layer, the metal-semiconductor compound layer including at least 1×1020 atoms/cm3 of S in the its whole depth, and a metal electrode formed on the metal-semiconductor compound layer.

Abstract: In one embodiment a heat exchanger assembly comprises at least one heat pipe and a casing which is to receive a blower, the casing comprising a plurality of heat exchanging plates, wherein at least one of the heat exchanging plates comprises at least one tongue which is to cover a portion of an exterior surface of the at least one heat pipe. Other embodiments may be described.

Abstract: A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.

Abstract: An electronic device is provided that includes a base having a first side and a second side, and a lid having a first side and a second side. The electronic device may also include a heat exchanger provided at the base. The heat exchanger may have a first surface exposed to outside the base.

Abstract: An electronic device is provided that includes a base having a top portion and a bottom portion. The bottom portion may include a first bottom part and a second bottom part. The first bottom part may form a first plane, and the second bottom part may form a second plane, the second plane being non-planar with the first plane. The second bottom part may include an input opening. The top portion of the base may include an output opening. The input opening and the output opening may allow air to flow from behind the electronic device to over the base.

Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a variable resistance layer. The variable resistance layer is provided between the first electrode and the second electrode. The variable resistance layer contains impurity of a nonmetallic element. The impurity is at least one selected from the group consisting of S, Se, Te, F, Cl, Br, and I.

Abstract: According to one embodiment, a memory device includes a first electrode, a second electrode, and a variable resistance film. The variable resistance film is connected between the first electrode and the second electrode. The first electrode includes a metal contained in a matrix made of a conductive material. A cohesive energy of the metal is lower than a cohesive energy of the conductive material. A concentration of the metal at a central portion of the first electrode in a width direction thereof is higher than concentrations of the metal in two end portions of the first electrode in the width direction.

Abstract: According to an embodiment, a semiconductor device includes first and second memristors. The first memristor includes a first electrode made of a first material, a second electrode made of a second material, and a first resistive switching film arranged between the first and second electrodes. The first resistive switching film is connected to both the first and second electrodes. The second memristor includes a third electrode made of a third material, a fourth electrode made of the second material, and a second resistive switching film arranged between the third and fourth electrodes. The second resistive switching film is connected to both the third and fourth electrodes. The work function of the first material is smaller than that of the second material. The work function of the third material is larger than that of the second material.

Abstract: According to an embodiment, a semiconductor memory device includes a controller and a second storage unit. The controller is configured to control a write process of writing data into a first storage unit in which data supplied from a host device are stored or a read process of reading the data stored in the first storage in response to a request from the host device. The second storage unit is temporarily used in the write process or the read process. The second storage unit includes a nonvolatile third storage unit having an area for storing a duplicate of the data to be written by the write process; and a nonvolatile fourth storage unit having a work area for the write process or the read process and having a higher read/write speed than the third storage unit.

Abstract: According to an embodiment, an error correction device includes first calculators, second calculators, estimators, and an inverter. Each first calculator calculates a first message representing a probability that 1-bit data that is input in a corresponding variable node is 1, Each second calculator calculates a second message representing a probability that a value of the data input to the variable node is 1 for each of two or more variable nodes connected to the check node by using the first, messages of the variable nodes connected to the check node. Each estimator estimates a true value of the data input to the variable node to generate an estimated value by using the first and second messages. The inverter inverts the estimated value associated with at least one of the variable nodes with a probability higher than 0 and lower than 1.

Abstract: One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

Abstract: An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

Abstract: A memory device includes a first electrode, a second electrode, a third electrode, a first variable resistance layer between the first electrode and the third electrode, and a second variable resistance layer between the second electrode and the third electrode. The first, second, and third electrodes, and the first and second variable resistance layers are formed of materials that cause the first variable resistance layer to transition from a high resistance state to a low resistance state when a voltage is applied across the first and second electrodes and maintain the high resistance state when the voltage is cut off, and cause the second variable resistance layer to transition from a high resistance state to a low resistance state when the voltage is applied across the first and second electrodes and transition from the high resistance state to the low resistance state when the voltage is cut off.