Patents by Inventor Yoshifumi Tomomatsu
Yoshifumi Tomomatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220376073Abstract: A Schottky barrier diode according to the present disclosure includes an n-type semiconductor substrate, one or more p-type guard rings provided on a side of an upper surface of the semiconductor substrate, an anode electrode provided on the upper surface of the semiconductor substrate, a cathode electrode provided on a rear surface of the semiconductor substrate and an insulating film provided on an inner guard ring on an innermost side among the one or more guard rings, wherein the anode electrode rides on the insulating film and has its end portion provided just above the inner guard ring, the anode electrode and the inner guard ring are provided away from each other, and a thickness of the insulating film is 1.0 ?m or more.Type: ApplicationFiled: January 14, 2020Publication date: November 24, 2022Applicant: Mitsubishi Electric CorporationInventors: Seiya NAKANO, Yoshifumi TOMOMATSU, Yasuo ATA
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Patent number: 10347725Abstract: An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer.Type: GrantFiled: December 2, 2015Date of Patent: July 9, 2019Assignee: Mitsubishi Electric CorporationInventors: Akihiko Nobukuni, Hirofumi Oki, Yoshifumi Tomomatsu
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Patent number: 9972618Abstract: An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer on a lower surface of the n-type drift layer. A FWD includes the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer. A p-type well is formed on the upper surface of the n-type drift layer in a wiring region and a termination region. A wiring is formed on the p-type well in the wiring region. The p-type well has a higher impurity concentration and is deeper than the p-type anode layer. The p-type well is not formed directly above the n-type cathode layer and is separate from a region directly above the n-type cathode layer.Type: GrantFiled: December 17, 2014Date of Patent: May 15, 2018Assignee: Mitsubishi Electric CorporationInventors: Hideki Haruguchi, Yoshifumi Tomomatsu
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Publication number: 20170162562Abstract: An IGBT includes an n-type drift layer, a p-type base layer and an n-type emitter layer formed on an upper surface of the n-type drift layer, and a p-type collector layer on a lower surface of the n-type drift layer. A FWD includes the n-type drift layer, a p-type anode layer formed on the upper surface of the n-type drift layer and an n-type cathode layer formed on the lower surface of the n-type drift layer. A p-type well is formed on the upper surface of the n-type drift layer in a wiring region and a termination region. A wiring is formed on the p-type well in the wiring region. The p-type well has a higher impurity concentration and is deeper than the p-type anode layer. The p-type well is not formed directly above the n-type cathode layer and is separate from a region directly above the n-type cathode layer.Type: ApplicationFiled: December 17, 2014Publication date: June 8, 2017Applicant: Mitsubishi Electric CorporationInventors: Hideki HARUGUCHI, Yoshifumi TOMOMATSU
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Publication number: 20160380068Abstract: An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer.Type: ApplicationFiled: December 2, 2015Publication date: December 29, 2016Applicant: Mitsubishi Electric CorporationInventors: Akihiko NOBUKUNI, Hirofumi OKI, Yoshifumi TOMOMATSU
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Patent number: 8791568Abstract: A semiconductor device includes a substrate, a surface electrode of aluminum-containing material formed on the substrate, a metal film of solderable material formed on the surface electrode, and an end-securing film securing an end of the metal film and having a portion on the surface electrode and also having an overlapping portion which is formed integrally with the portion on the surface electrode and which overlaps the end of the metal film.Type: GrantFiled: March 2, 2012Date of Patent: July 29, 2014Assignee: Mitsubishi Electric CorporationInventors: Seiya Nakano, Yoshifumi Tomomatsu
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Publication number: 20120306079Abstract: A semiconductor device includes a substrate, a surface electrode of aluminum-containing material formed on the substrate, a metal film of solderable material formed on the surface electrode, and an end-securing film securing an end of the metal film and having a portion on the surface electrode and also having an overlapping portion which is formed integrally with the portion on the surface electrode and which overlaps the end of the metal film.Type: ApplicationFiled: March 2, 2012Publication date: December 6, 2012Applicant: Mitsubishi Electric CorporationInventors: Seiya NAKANO, Yoshifumi Tomomatsu
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Patent number: 8294244Abstract: A semiconductor device comprises: a semiconductor substrate; a plurality of IGBT cells on the semiconductor substrate, each of the IGBT cells including a gate electrode and a first emitter electrode; a first gate wiring on the substrate and being connected to the gate electrode; an interlayer insulating film covering the first emitter electrode and the first gate wiring; and a second emitter electrode on the interlayer insulating film and being connected to the first emitter electrode through an opening of the interlayer insulating film, wherein the second emitter electrode extends above the first gate wiring via the interlayer insulating film.Type: GrantFiled: March 11, 2010Date of Patent: October 23, 2012Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Yoshifumi Tomomatsu
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Patent number: 8178947Abstract: There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 ?m.Type: GrantFiled: October 1, 2008Date of Patent: May 15, 2012Assignee: Mitsubishi Electric CorporationInventors: Tetsuo Takahashi, Yoshifumi Tomomatsu
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Patent number: 7986003Abstract: A carrier storage layer is located in a region of a predetermined depth from a surface of an N? substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N? substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N? substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.Type: GrantFiled: July 26, 2007Date of Patent: July 26, 2011Assignee: Mitsubishi Electric CorporationInventors: Shinji Aono, Hideki Takahashi, Yoshifumi Tomomatsu, Junichi Moritani
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Publication number: 20110049562Abstract: A semiconductor device comprises: a semiconductor substrate; a plurality of IGBT cells on the semiconductor substrate, each of the IGBT cells including a gate electrode and a first emitter electrode; a first gate wiring on the substrate and being connected to the gate electrode; an interlayer insulating film covering the first emitter electrode and the first gate wiring; and a second emitter electrode on the interlayer insulating film and being connected to the first emitter electrode through an opening of the interlayer insulating film, wherein the second emitter electrode extends above the first gate wiring via the interlayer insulating film.Type: ApplicationFiled: March 11, 2010Publication date: March 3, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenji SUZUKI, Yoshifumi Tomomatsu
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Patent number: 7768101Abstract: A p-type collector region of an IGBT and an n-type cathode region of a free wheel diode are alternately formed in a second main surface of a semiconductor substrate. A back electrode is formed on the second main surface so as to be in contact with both of the p-type collector region and the n-type cathode region, and has a titanium layer, a nickel layer and a gold layer that are successively stacked from the side of the second main surface. A semiconductor device capable of obtaining a satisfactory ON voltage in any of conduction of an insulated gate field effect transistor and conduction of the free wheel diode as well as a manufacturing method thereof can thus be obtained.Type: GrantFiled: March 12, 2007Date of Patent: August 3, 2010Assignee: Mitsubishi Electric CorporationInventors: Kenji Suzuki, Hideki Takahashi, Yoshifumi Tomomatsu
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Patent number: 7705398Abstract: A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region with the second impurity region. A control electrode layer is opposite to the second impurity region with an insulating film interposed. That portion of the second main surface which is opposite to the portion of the first main surface where the first impurity region is formed surrounds the regions for forming the fourth and fifth impurity regions of the second main surface, and it is a region of the first conductivity type or a region of the second conductivity type having impurity concentration not higher than that of the first impurity region.Type: GrantFiled: December 29, 2006Date of Patent: April 27, 2010Assignee: Mitsubishi Electric CorporationInventors: Mitsuru Kaneda, Hideki Takahashi, Yoshifumi Tomomatsu
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Publication number: 20090283797Abstract: There is provided a semiconductor device in which an amount of fluctuations in output capacitance and feedback capacitance is reduced. In a trench-type insulated gate semiconductor device, a width of a portion of an electric charge storage layer in a direction along which a gate electrode and a dummy gate are aligned is set to be at most 1.4 ?m.Type: ApplicationFiled: October 1, 2008Publication date: November 19, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Tetsuo TAKAHASHI, Yoshifumi Tomomatsu
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Publication number: 20080197379Abstract: A carrier storage layer is located in a region of a predetermined depth from a surface of an N? substrate, a base region is located in a shallower region than the predetermined depth and an emitter region is located in a surface of the N? substrate. The carrier storage layer is formed by phosphorus injected to have a maximum impurity concentration at the predetermined depth, the base region is formed by boron injected to have the maximum impurity concentration at a shallower position than the predetermined depth and the emitter region is formed by arsenic injected to have the maximum impurity concentration at the surface of the N? substrate. An opening is formed to extend through the emitter region, base region and the carrier storage layer. On the inner wall of the opening, a gate electrode is formed with a gate insulating film therebetween.Type: ApplicationFiled: July 26, 2007Publication date: August 21, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shinji AONO, Hideki Takahashi, Yoshifumi Tomomatsu, Junichi Moritani
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Publication number: 20080102576Abstract: A p-type collector region of an IGBT and an n-type cathode region of a free wheel diode are alternately formed in a second main surface of a semiconductor substrate. A back electrode is formed on the second main surface so as to be in contact with both of the p-type collector region and the n-type cathode region, and has a titanium layer, a nickel layer and a gold layer that are successively stacked from the side of the second main surface. A semiconductor device capable of obtaining a satisfactory ON voltage in any of conduction of an insulated gate field effect transistor and conduction of the free wheel diode as well as a manufacturing method thereof can thus be obtained.Type: ApplicationFiled: March 12, 2007Publication date: May 1, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kenji Suzuki, Hideki Takahashi, Yoshifumi Tomomatsu
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Publication number: 20080093697Abstract: A second impurity region is surrounded by a first impurity region at a first main surface. A third impurity region of the first main surface sandwiches the second impurity region with the first impurity region. Fourth and fifth impurity regions of a second main surface sandwich the first impurity region with the second impurity region. A control electrode layer is opposite to the second impurity region with an insulating film interposed. That portion of the second main surface which is opposite to the portion of the first main surface where the first impurity region is formed surrounds the regions for forming the fourth and fifth impurity regions of the second main surface, and it is a region of the first conductivity type or a region of the second conductivity type having impurity concentration not higher than that of the first impurity region.Type: ApplicationFiled: December 29, 2006Publication date: April 24, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Mitsuru Kaneda, Hideki Takahashi, Yoshifumi Tomomatsu
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Patent number: 7211837Abstract: A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1 and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2 in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2. Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.Type: GrantFiled: March 11, 2005Date of Patent: May 1, 2007Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshifumi Tomomatsu, Hideki Takahashi, Chihiro Tadokoro
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Publication number: 20070069252Abstract: The gate of an IGBT is connected to a gate terminal. One end of a clamping element is connected to an anode terminal. A voltage higher than a clamping voltage is applied between the gate and the emitter, to thereby test the dielectric breakdown voltage of a gate insulating film of the IGBT. The IGBT is eliminated which has a gate insulating film at a dielectric breakdown voltage failing to fall within its proper distribution range. Thereafter, a gate terminal and an anode terminal are wire bonded in the normal IGBT.Type: ApplicationFiled: November 28, 2006Publication date: March 29, 2007Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Chihiro Tadokoro, Yoshifumi Tomomatsu
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Publication number: 20050263853Abstract: A CSTBT includes a carrier stored layer (113) formed between a P base region (104) and a semiconductor substrate (103) and the carrier stored layer has an impurity concentration higher than that of the semiconductor substrate (103). The P base region (104) in a periphery of a gate electrode (110) functions as a channel. When it is assumed that an impurity concentration of a first carrier stored layer region (113a) just under the channel is ND1 and an impurity concentration of a second carrier stored layer region (113b) other than just under the channel is ND2 in the carrier stored layer (113), the relationship of the impurity concentrations is defined by ND1<ND2. Thus, a gate capacity and a short-circuit current can be controlled and variation in threshold voltage can be prevented.Type: ApplicationFiled: March 11, 2005Publication date: December 1, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Yoshifumi Tomomatsu, Hideki Takahashi, Chihiro Tadokoro