Abstract: An IGBT module is configured with a plurality of IGBT cells connected to each other. The IGBT chips are each configured a plurality of unit cells connected to each other. The unit cells each include one IGBT element. Gate voltage is applied to the gate of the IGBT element from a common gate terminal through a gate pad and a gate resistor. Emitter voltage is applied to the emitter of the IGBT element from a common emitter terminal through an emitter pad. Collector voltage is applied to the collector of the IGBT element from a common collector terminal. The gate pad, gate transistor and emitter pad are provided for each of the unit cells. Thus obtained is an IGBT module capable of suppressing gate voltage oscillation without significantly increasing switching loss.

Abstract: The gate of an IGBT is connected to a gate terminal. One end of a clamping element is connected to an anode terminal. A voltage higher than a clamping voltage is applied between the gate and the emitter, to thereby test the dielectric breakdown voltage of a gate insulating film of the IGBT. The IGBT is eliminated which has a gate insulating film at a dielectric breakdown voltage failing to fall within its proper distribution range. Thereafter, a gate terminal and an anode terminal are wire bonded in the normal IGBT.

Abstract: In an insulated gate semiconductor device having first, second and third gate electrodes (10) which are buried in first, second, and third trenches (7), an emitter electrode (11) is commonly connected to a base region (4), an emitter region (5) and the second gate electrode (10b), and the third gate electrode (10c) is connected to only the first gate electrode (10a). An insulating interlayer (9) interposed between the emitter electrode (11) and the gate electrodes (10) has a pattern configuration such that the second gate electrode is partially connected to the emitter electrode, to thereby control a gate capacity and suppress a short-circuit current caused by a crack.

Abstract: An insulated gate bipolar transistor, a semiconductor device using such a transistor, and manufacturing methods of these. The transistor, device, and method eliminate the necessity of connection to a freewheel diode used for bypassing a circulating current. In the transistor, device, and method the concentration of impurities of an N+ buffer layer that forms a junction with a P+ collector layer is increased so that it is possible to reduce an avalanche breakdown voltage of a parasitic diode formed by an N base layer and the P+ collector layer. Thus, the reverse voltage resistance of an IGBT is lowered to not more than 5 times the collector-emitter saturated voltage.

Abstract: One aspect of the present invention is a to provide a process for manufacturing a pn junction diode, includes providing a semiconductor wafer having an n-type cathode layer formed thereon. Then, a p-type anode layer is formed on the n-type cathode layer so that a pn junction interface is formed between the n-type cathode layer and the p-type anode layer. Next, a cathode and anode electrodes are formed on the semiconductor wafer and the p-type anode layer, respectively. Lastly, first and second ions having average projection ranges Rp different from each other are simultaneously implanted up to the cathode layer so that one or more first and second implanted regions are formed alternately and overlapped side by side, thereby forming a lattice-defect region having a substantially uniform thickness beneath and adjacent to the pn junction interface.

Abstract: A semiconductor device capable of lowering the ON voltage by decreasing the area of the invalid region compared to that of prior art yet maintaining the ability for suppressing the latch-up comparable to that of the conventional IGBTS. The semiconductor device comprises a semiconductor layer of a first conductivity type, a collector layer of a second conductivity type formed on one surface of the semiconductor layer, a base layer of the second conductivity type formed on the other surface of the semiconductor layer, and an emitter layer of the first conductivity type formed in the base layer, wherein the emitter layer having the shape of a ladder being constituted by two crossbeams and cleats formed between the crossbeams, the cleat being provided even between facing end portions of the two crossbeams.

Abstract: A semiconductor device has a first IGBT (1) for controlling a principal current and a second IGBT (2) for preventing an over-current of the first IGBT (1). A diode portion (11) is disposed between the emitter (5) of the first IGBT (1) and the emitter (6) of the second IGBT (2) so as to be in parallel with a sensing resistor (8). The diode portion (11) is composed of a first diode (9) and a second diode (10), which are connected in reverse series to each other. In order to prevent the over-current of the first IGBT (1) and the destruction of the second IGBT (2), each of the diodes (9, 10) has a breakdown voltage in the reverse voltage direction, which is lower than the endurance voltage between the emitters (5, 6) and is higher than the upper limit of the voltage sensed by the sensing resistor (8).

Abstract: The present invention relates to a technique of limiting an overcurrent of a power semiconductor element (1) such as an IGBT. In a background art overcurrent protection circuit (10P), when an emitter current (i) and a current sense current (is) do not show the same behavior even in a transient state, the current sense current tends to momentarily increase at a turnoff, and in such a case, the energizing capability of a MOSFET (2P) in the overcurrent protection circuit increases and the turnoff speed of an IGBT (1P) becomes much faster than necessary and as a result, a surge voltage disadvantageously increases. Then, in the present invention, a diode (5) having a forward voltage set not lower than a threshold voltage of the MOSFET (2) is so provided as a voltage clamping circuit (4) between a gate electrode (2G) and a source electrode (2S) as to be biased in the forward direction in an overcurrent protection circuit (10) of an IGBT (1).

Abstract: A semiconductor device has a first IGBT (1) for controlling a principal current and a second IGBT (2) for preventing an over-current of the first IGBT (1). A diode portion (11) is disposed between the emitter (5) of the first IGBT (1) and the emitter (6) of the second IGBT (2) so as to be in parallel with a sensing resistor (8). The diode portion (11) is composed of a first diode (9) and a second diode (10), which are connected in reverse series to each other. In order to prevent the over-current of the first IGBT (1) and the destruction of the second IGBT (2), each of the diodes (9, 10) has a breakdown voltage in the reverse voltage direction, which is lower than the endurance voltage between the emitters (5, 6) and is higher than the upper limit of the voltage sensed by the sensing resistor (8).

Abstract: In an insulated gate semiconductor device having first, second and third gate electrodes (10) which are buried in first, second, and third trenches (7), an emitter electrode (11) is commonly connected to a base region (4), an emitter region (5) and the second gate electrode (10b), and the third gate electrode (10c) is connected to only the first gate electrode (10a). An insulating interlayer (9) interposed between the emitter electrode (11) and the gate electrodes (10) has a pattern configuration such that the second gate electrode is partially connected to the emitter electrode, to thereby control a gate capacity and suppress a short-circuit current caused by a crack.

Abstract: One aspect of the present invention is a to provide a process for manufacturing a pn junction diode, includes providing a semiconductor wafer having an n-type cathode layer formed thereon. Then, a p-type anode layer is formed on the n-type cathode layer so that a pn junction interface is formed between the n-type cathode layer and the p-type anode layer. Next, a cathode and anode electrodes are formed on the semiconductor wafer and the p-type anode layer, respectively. Lastly, first and second ions having average projection ranges Rp different from each other are simultaneously implanted up to the cathode layer so that one or more first and second implanted regions are formed alternately and overlapped side by side, thereby forming a lattice-defect region having a substantially uniform thickness beneath and adjacent to the pn junction interface.

Abstract: In a field effect semiconductor device in which switching is performed by a gate voltage inputted from outside via a gate resistance circuit for restricting charging and discharge currents flowing between an insulated gate and an emitter, the improvement comprises: an insulated gate electrode portion which is formed by a gate electrode pad and a gate electrode insulated from the gate electrode pad; the gate resistance circuit being inserted between the gate electrode pad and the gate electrode so as to be formed integrally with the insulated gate electrode portion; and the gate resistance circuit comprising a first gate resistance and a first series circuit connected to the first gate resistance in parallel and including a second gate resistance and a first diode such that an anode of the first diode is connected to the gate electrode.

Abstract: This invention relates to an insulated gate bipolar transistor, a semiconductor device using such a transistor and manufacturing methods of these, and in particular, its object is to eliminate the necessity of connection to a freewheel diode used for bypassing a circulating current.

Abstract: A power semiconductor device includes a power semiconductor element formed on a substrate and a temperature detector including a temperature detecting diode element having at least one diode for detecting temperature formed on the substrate. Additionally, the temperature detecting diode includes two regions having different conductive type each other. The capacitance between one region and base region of the semiconductor element is as large as capacitance between another region and the base region.

Abstract: The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly, an object of the present invention is to reduce an ON voltage while ensuring a wide operating area and sustaining a high breakdown voltage. To achieve this object, a semiconductor base body is divided into a first MOS region and a second MOS region. In the first MOS region, a p base layer, an n+ emitter layer and a p+ layer are provided in an upper main surface of the semiconductor base body. In the second MOS region, a p base layer, an n layer and a p+ layer are provided. When a positive gate voltage is applied to a gate electrode in order to turn on the device, since the p base layer and the emitter electrode are cut off, a main current does not flow in the p base layer. Therefore, a hole accumulation effect is enhanced and the ON voltage is reduced.

Abstract: A semiconductor device includes an insulating substrate for electrical insulation formed of a single-crystal silicon chip as a base, an electrode pattern formed on the insulating substrate to allow electric current to pass therethrough, and a plurality of semiconductor elements selectively mounted on the electrode pattern. The plurality of semiconductor elements and the electrode pattern are selectively electrically connected to each other.

Abstract: A power semiconductor device includes a power semiconductor element formed on a substrate and a temperature detector including a temperature detecting diode element having at least one diode for detecting temperature formed on the substrate. Additionally, the temperature detecting diode includes two regions having different conductive type each other. The capacitance between one region and base region of the semiconductor element is as large as capacitance between another region and the base region.

Abstract: In a field effect semiconductor device in which switching is performed by a gate voltage inputted from outside via a gate resistance circuit for restricting charging and discharge currents flowing between an insulated gate and an emitter, the improvement comprises: an insulated gate electrode portion which is formed by a gate electrode pad and a gate electrode insulated from the gate electrode pad; the gate resistance circuit being inserted between the gate electrode pad and the gate electrode so as to be formed integrally with the insulated gate electrode portion; and the gate resistance circuit comprising a first gate resistance and a first series circuit connected to the first gate resistance in parallel and including a second gate resistance and a first diode such that an anode of the first diode is connected to the gate electrode.

Abstract: A field-effect semiconductor device having a semiconductor layer of a first conductivity type, a collector region of a second conductivity type that is formed beneath the semiconductor layer and equipped with a collector electrode on its lower surface, a base region of the second conductivity type that is formed as part of the upper surface of the semiconductor layer, at least one pair of emitter regions of the first conductivity type that are formed as part of the upper surface of the base region, an insulating layer that is formed to contact the base region that is located between the emitter regions and the semiconductor layer, a gate electrode that is placed on the upper surface of the insulating layer, an interlayer insulating film that is formed to cover the gate electrode, a barrier metal layer that is formed to continuously contact the interlayer insulating film, base region, and emitter region, and an emitter electrode that is formed on the upper surface of the barrier metal layer.

Abstract: The semiconductor device includes a semiconductor base body (11) formed of a damaged layer (102) serving as a gettering layer, a P+ collector layer (103), an N+ buffer layer (104), and an N− layer (105) laid one on top of another, a gate electrode (27) selectively formed on the upper main surface of the semiconductor base body (11) specifically on the external main surface of the N− layer (105), with a gate insulating film (26) interposed therebetween, an emitter electrode (28) selectively formed on the upper main surface of the semiconductor base body (11), and a collector electrode (106) formed on the lower main surface of the semiconductor base body (11), specifically on the external main surface of the damaged layer (102).