Patents by Inventor Yoshiharu Kato

Yoshiharu Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240026603
    Abstract: A synthetic leather according to an embodiment includes: a fibrous substrate; an adhesive layer containing a yellowing-resistant polycarbonate-based polyurethane resin and/or a yellowing polycarbonate-based polyurethane resin; and a skin layer that contains a yellowing-resistant polycarbonate-based polyurethane resin and that is laminated on the fibrous substrate via the adhesive layer. The synthetic leather has excellent oleic acid resistance.
    Type: Application
    Filed: December 24, 2021
    Publication date: January 25, 2024
    Applicant: SEIREN CO., LTD.
    Inventors: Yasuki NABATA, Yoshiharu KATO
  • Publication number: 20230335599
    Abstract: A device includes a substrate with upper/lower surfaces, including hydrogen containing region having hydrogen chemical concentration peaks in a depth direction. A carrier concentration distribution of the hydrogen containing region includes a first carrier concentration peak, a second carrier concentration peak closest to the first carrier concentration peak, a third carrier concentration peak arranged closer to the upper surface than the second carrier concentration peak, a first inter peak region arranged between the first and second carrier concentration peaks, a second inter peak region arranged between the second and third carrier concentration peaks, and an inter-peaks concentration peak arranged in the second inter peak region such that the concentration peak does not overlap the hydrogen chemical concentration peaks in the second and third carrier concentration peaks. A local minimum value of a carrier concentration in the first inter peak region is smaller than that of the second inter peak region.
    Type: Application
    Filed: June 13, 2023
    Publication date: October 19, 2023
    Inventors: Yoshiharu KATO, Toru AJIKI, Tohru SHIRAKAWA, Misaki TAKAHASHI, Kaname MITSUZUKA, Takashi YOSHIMURA, Yuichi ONOZAWA, Hiroshi TAKISHITA, Soichi YOSHIDA
  • Patent number: 11715771
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate includes a hydrogen containing region including hydrogen, and the hydrogen containing region includes a high concentration region with a higher carrier concentration than a virtual carrier concentration determined based on a concentration of hydrogen included and an activation ratio of hydrogen. The semiconductor substrate includes an N type drift region, an N type emitter region that has a higher carrier concentration than that in the drift region, a P type base region, a P type collector region provided to be in contact with a lower surface of the semiconductor substrate, and an N type buffer region that is provided between the collector region and the drift region, and has a higher carrier concentration than that in the drift region, and the hydrogen containing region is included in the buffer region.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 1, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiharu Kato, Toru Ajiki, Tohru Shirakawa, Misaki Takahashi, Kaname Mitsuzuka, Takashi Yoshimura, Yuichi Onozawa, Hiroshi Takishita, Soichi Yoshida
  • Patent number: 11532737
    Abstract: A semiconductor device is provided, wherein a semiconductor substrate includes: a first trench portion provided from a front surface of the semiconductor substrate to a predetermined depth, and having a longer portion and a shorter portion as seen from above; and a first conductivity-type floating semiconductor region at least partially exposed on the front surface and surrounded by the first trench portion, an interlayer insulating film has openings to electrically connect an emitter electrode and the floating semiconductor region, the openings include: a first opening closest to an outer end of the floating semiconductor region in a direction parallel to the longer portion; and a second opening second closest to the outer end in the direction parallel to the longer portion, and a distance between the first opening and the second opening is shorter than a distance between any adjacent two of the openings other than the first opening.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 20, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiharu Kato, Hidenori Takahashi, Tatsuya Naito
  • Publication number: 20220181472
    Abstract: Provided is a semiconductor device comprising: a semiconductor substrate provided with a drift region; a buffer region arranged between the drift region and the lower surface, wherein a doping concentration distribution has three or more concentration peaks; and a collector region arranged between the buffer region and the lower surface, wherein the three or more concentration peaks in the buffer region include: a first concentration peak closest to the lower surface; a second concentration peak closest, next to the first concentration peak, to the lower surface, arranged 5 ?m or more distant from the lower surface in the depth direction, and having a doping concentration lower than the first concentration peak, the doping concentration being less than 1.0×1015/cm3; and a high concentration peak arranged farther from the lower surface than the second concentration peak, and having a higher doping concentration than the second concentration peak.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Inventors: Yoshiharu KATO, Yosuke SAKURAI, Seiji NOGUCHI, Takashi YOSHIMURA
  • Publication number: 20220084880
    Abstract: To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Yoshiharu KATO, Tohru SHIRAKAWA
  • Publication number: 20220084826
    Abstract: Provided is a semiconductor device comprising: a semiconductor substrate; a plurality of peaks of a doping concentration provided on a back surface of the semiconductor substrate; and a flat part, with a doping concentration more than or equal to 2.5 times a substrate concentration of the semiconductor substrate, provided between the plurality of peaks in a depth direction of the semiconductor substrate, wherein at least one of the plurality of peaks is a first peak provided on a front surface side relative to the flat part, wherein a doping concentration of the first peak is less than or equal to twice the doping concentration of the flat part.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 17, 2022
    Inventors: Yoshiharu KATO, Toru AJIKI, Takashi YOSHIMURA
  • Patent number: 11195749
    Abstract: To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: December 7, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiharu Kato, Tohru Shirakawa
  • Publication number: 20210359088
    Abstract: Provided is a semiconductor device, including: a drift region of a first conductivity type which is provided in a semiconductor substrate, and a buffer region of the first conductivity type which is provided between the drift region and a lower surface of the semiconductor substrate, and has three or more concentration peaks higher than a doping concentration of the drift region of the semiconductor substrate in a depth direction. Three or more of the concentration peaks includes a shallowest peak closest to the lower surface of the semiconductor substrate, a high concentration peak arranged at an upper side than the lower surface of the semiconductor substrate than the shallowest peak, and one or more low concentration peaks arranged at an upper side than the lower surface of the semiconductor substrate than the high concentration peak and of which the doping concentration is ? or less of the high concentration peak.
    Type: Application
    Filed: July 27, 2021
    Publication date: November 18, 2021
    Inventors: Kota OHI, Yoshihiro IKURA, Yosuke SAKURAI, Mutsumi KITAMURA, Yuichi ONOZAWA, Yoshiharu KATO, Toru AJIKI
  • Publication number: 20210043739
    Abstract: Provided is a semiconductor device comprising a semiconductor substrate, wherein the semiconductor substrate includes a hydrogen containing region including hydrogen, and the hydrogen containing region includes a high concentration region with a higher carrier concentration than a virtual carrier concentration determined based on a concentration of hydrogen included and an activation ratio of hydrogen. The semiconductor substrate includes an N type drift region, an N type emitter region that has a higher carrier concentration than that in the drift region, a P type base region, a P type collector region provided to be in contact with a lower surface of the semiconductor substrate, and an N type buffer region that is provided between the collector region and the drift region, and has a higher carrier concentration than that in the drift region, and the hydrogen containing region is included in the buffer region.
    Type: Application
    Filed: October 22, 2020
    Publication date: February 11, 2021
    Inventors: Yoshiharu KATO, Toru AJIKI, Tohru SHIRAKAWA, Misaki TAKAHASHI, Kaname MITSUZUKA, Takashi YOSHIMURA, Yuichi ONOZAWA, Hiroshi TAKISHITA, Soichi YOSHIDA
  • Patent number: 10600897
    Abstract: In an edge termination region, in a carrier drawing region between an active region and a gate runner part, a p+-type contact region is provided in a surface region of a p-type well region. In the carrier drawing region, in second contact holes formed an interlayer insulating film, a contact plug is embedded in each via the barrier metal, and contacts of the p+-type contact region and the barrier metal at an emitter electric potential are formed. The contacts of the carrier drawing region are disposed in a striped layout extending along an outer periphery of the active region; the contacts surround the active region. A contact resistance of the contacts of the carrier drawing region is higher than a contact resistance of a contact (emitter contact) of a MOS gate.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: March 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru Shirakawa, Yoshiharu Kato
  • Patent number: 10545866
    Abstract: Disclosed is an improved approach to implement training for memory technologies, where a data valid window is re-determined using boundary information for a new data valid window. The information obtained for the new location of the first edge is used to minimize the computational resources required to identify the location of the second edge. This greatly improves the efficiency of the process to perform the re-training.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 28, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Yoshiharu Kato, Manas Lahon, Sandeep Brahmadathan
  • Publication number: 20200020579
    Abstract: To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.
    Type: Application
    Filed: June 3, 2019
    Publication date: January 16, 2020
    Inventors: Yoshiharu KATO, Tohru SHIRAKAWA
  • Patent number: 10304948
    Abstract: To provide a semiconductor device in which an edge termination structure can be made smaller easily. A semiconductor device is provided, the semiconductor device including an active region and an edge termination structure formed on a front surface side of a semiconductor substrate, wherein an edge termination structure has a guard ring provided surrounding an active region on a front surface side of a semiconductor substrate, a first field plate provided on a front surface side of a guard ring, an electrode unit provided on a front surface side of a first field plate, a second field plate provided between a first field plate and a electrode unit, and a conductive connecting unit which mutually electrically connects a first field plate, an electrode unit, a second field plate, and a guard ring.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: May 28, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yoshiharu Kato, Hidenori Takahashi
  • Publication number: 20190140084
    Abstract: In an edge termination region, in a carrier drawing region between an active region and a gate runner part, a p+-type contact region is provided in a surface region of a p-type well region. In the carrier drawing region, in second contact holes formed an interlayer insulating film, a contact plug is embedded in each via the barrier metal, and contacts of the p+-type contact region and the barrier metal at an emitter electric potential are formed. The contacts of the carrier drawing region are disposed in a striped layout extending along an outer periphery of the active region; the contacts surround the active region. A contact resistance of the contacts of the carrier drawing region is higher than a contact resistance of a contact (emitter contact) of a MOS gate.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 9, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Tohru SHIRAKAWA, Yoshiharu KATO
  • Publication number: 20180269315
    Abstract: A semiconductor device is provided, wherein a semiconductor substrate includes: a first trench portion provided from a front surface of the semiconductor substrate to a predetermined depth, and having a longer portion and a shorter portion as seen from above; and a first conductivity-type floating semiconductor region at least partially exposed on the front surface and surrounded by the first trench portion, an interlayer insulating film has openings to electrically connect an emitter electrode and the floating semiconductor region, the openings include: a first opening closest to an outer end of the floating semiconductor region in a direction parallel to the longer portion; and a second opening second closest to the outer end in the direction parallel to the longer portion, and a distance between the first opening and the second opening is shorter than a distance between any adjacent two of the openings other than the first opening.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 20, 2018
    Inventors: Yoshiharu KATO, Hidenori TAKAHASHI, Tatsuya NAITO
  • Patent number: 9906849
    Abstract: Provided is a sound-transmitting waterproof film having waterproof performance and stable sound-transmitting performance in a wide tonal range. The sound-transmitting waterproof film includes a porous film of a synthetic resin, and has a water pressure resistance of 10 to 400 kPa in accordance with a JIS L 1092 method B (a high water pressure method) and has an acoustic loss of less than 10 dB at a frequency of 1 kHz, an acoustic loss of less than 5 dB at a frequency of 2 kHz, and an acoustic loss of less than 5 dB at a frequency of 5 kHz in sound-transmitting performance tests.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: February 27, 2018
    Assignee: Seiren Co., Ltd.
    Inventors: Yoshiharu Kato, Katsumi Sakamoto, Yoshiyuki Yamada, Naoya Kishimoto
  • Publication number: 20170110560
    Abstract: To provide a semiconductor device in which an edge termination structure can be made smaller easily. A semiconductor device is provided, the semiconductor device including an active region and an edge termination structure formed on a front surface side of a semiconductor substrate, wherein an edge termination structure has a guard ring provided surrounding an active region on a front surface side of a semiconductor substrate, a first field plate provided on a front surface side of a guard ring, an electrode unit provided on a front surface side of a first field plate, a second field plate provided between a first field plate and a electrode unit, and a conductive connecting unit which mutually electrically connects a first field plate, an electrode unit, a second field plate, and a guard ring.
    Type: Application
    Filed: December 26, 2016
    Publication date: April 20, 2017
    Inventors: Yoshiharu KATO, Hidenori TAKAHASHI
  • Publication number: 20170091623
    Abstract: A creativity support server extracts a node that is generated by a user from a tree diagram that is generated according to nodes each representing an opinion created by each user to derive a solution to a problem dealt with in a discussion and links each representing relevance between the nodes. The creativity support server classifies the extracted node according to dependency between the extracted node and other nodes included in the tree diagram. The creativity support server specifies a character of the user according to result of the classifying.
    Type: Application
    Filed: August 29, 2016
    Publication date: March 30, 2017
    Inventors: Yoshiharu Kato, Masafumi Yano
  • Publication number: 20170091307
    Abstract: A creativity aiding server selects nodes from among a plurality of nodes included in a tree diagram that is generated according to nodes each representing an opinion created by each user to derive a solution to a problem dealt with in a discussion and links each representing relevance between the nodes, by tracking links backward from a solution node representing the solution to an assignment node representing an assignment, the selected nodes being included between the solution node and the assignment node. The creativity aiding server calculates a degree of contribution made by each of the selected nodes in deriving the solution, by using types of the selected nodes and types of the links. The creativity aiding server identifies one or more of the nodes of which the degree of contribution is equal to or higher than a threshold value.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 30, 2017
    Inventors: Yoshiharu Kato, Masafumi Yano