Patents by Inventor Yoshiharu Kato
Yoshiharu Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160337737Abstract: Provided is a sound-transmitting waterproof film having waterproof performance and stable sound-transmitting performance in a wide tonal range. The sound-transmitting waterproof film includes a porous film of a synthetic resin, and has a water pressure resistance of 10 to 400 kPa in accordance with a JIS L 1092 method B (a high water pressure method) and has an acoustic loss of less than 10 dB at a frequency of 1 kHz, an acoustic loss of less than 5 dB at a frequency of 2 kHz, and an acoustic loss of less than 5 dB at a frequency of 5 kHz in sound-transmitting performance tests.Type: ApplicationFiled: January 8, 2015Publication date: November 17, 2016Inventors: Yoshiharu KATO, Katsumi SAKAMOTO, Yoshiyuki YAMADA, Naoya KISHIMOTO
-
Patent number: 9206546Abstract: A moisture-permeable waterproof fabric which has a well-balanced combination of moisture permeability and waterproofing properties and has excellent strength, in particular, tensile strength, is provided without increasing environmental burden. A synthetic-polymer solution comprising a synthetic polymer consisting mainly of a polyurethane, fine inorganic particles, and a polar organic solvent is applied to one surface of a fibrous fabric and then brought into contact with a gaseous phase in which waterdrops having an average particle diameter of 1-30 ?m have been evenly dispersed, thereby making the synthetic polymer semisolid. The fabric is then immersed in water to completely solidify the polymer and thereby obtain a moisture-permeable waterproof fabric comprising the fibrous fabric and, united to one surface thereof, a microporous film of a single-layer structure comprising the synthetic polymer consisting mainly of a polyurethane (the number of micropores having a pore diameter of 0.Type: GrantFiled: April 28, 2010Date of Patent: December 8, 2015Assignee: SEIREN CO., LTD.Inventors: Yoshiharu Kato, Katsumi Sakamoto
-
Patent number: 8928397Abstract: A semiconductor device includes first and second resistors. The first resistor is formed in a first substrate region and coupled between a first node and an output node. The second resistor is formed in a second substrate region and coupled between the output node and a second node. The first substrate region is coupled to the first node which has a first voltage. The second node has a second voltage. The second substrate region is coupled to a voltage dividing node that is set in the first resistor.Type: GrantFiled: August 1, 2012Date of Patent: January 6, 2015Assignee: Spansion LLCInventors: Kazushi Kodera, Yoshiharu Kato
-
Patent number: 8878336Abstract: A fuse includes a first conductor, an insulating film on the first conductor, a second conductor on the insulating film, a first plug coupled to the first conductor, a second plug and a third plug each coupled to the second conductor, and a cover film formed on the second conductor and having tensile strength.Type: GrantFiled: August 21, 2012Date of Patent: November 4, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Makoto Yasuda, Kazuyoshi Arimura, Yoshiharu Kato
-
Patent number: 8711643Abstract: A memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit detects a logic level of the data strobe signal, which is driven by the memory, in accordance with the data read command.Type: GrantFiled: November 18, 2011Date of Patent: April 29, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Yoshiharu Kato
-
Patent number: 8560993Abstract: An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC0 and DC1 produce delay data strobe signals IDQS0 and IDQS1 delayed by delay times DT0 and DT1. Outputted as a reverse signal from the inverter INV0, is a reverse data strobe signal RIDQS0 in response to the delay data strobe signal IDQS0, and delayed by an allowable delay time IT. Inputted into the NAND gate ND0, are the reverse data strobe signal RIDQS0 and the delay data strobe signal IDQS1. When, in comparison with the phase of the delay data strobe signal IDQS0, the phase of the delay data strobe signal IDQS1 is delayed by the allowable delay time IT or more, a pulse signal PL0 is not outputted from the NAND gate ND0.Type: GrantFiled: June 26, 2009Date of Patent: October 15, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Yoshiharu Kato
-
Publication number: 20130049165Abstract: A fuse includes a first conductor, an insulating film on the first conductor, a second conductor on the insulating film, a first plug coupled to the first conductor, a second plug and a third plug each coupled to the second conductor, and a cover film formed on the second conductor and having tensile strength.Type: ApplicationFiled: August 21, 2012Publication date: February 28, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Makoto Yasuda, Kazuyoshi Arimura, Yoshiharu Kato
-
Publication number: 20130038385Abstract: A semiconductor device includes first and second resistors. The first resistor is formed in a first substrate region and coupled between a first node and an output node. The second resistor is formed in a second substrate region and coupled between the output node and a second node. The first substrate region is coupled to the first node which has a first voltage. The second node has a second voltage. The second substrate region is coupled to a voltage dividing node that is set in the first resistor.Type: ApplicationFiled: August 1, 2012Publication date: February 14, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Kazushi Kodera, Yoshiharu Kato
-
Publication number: 20120322328Abstract: Disclosed is a moisture-permeable waterproof fabric which is produced by using a plant-based material and has equivalent or superior performance as compared to conventional petroleum-based polyurethane resins. The moisture-permeable waterproof fabric comprises, on at least one surface thereof, a porous resin film composed of a polyurethane resin containing 5 to 80% by weight of a sebacic acid-based polyol component produced from a plant-based sebacic acid, and has an A-1 moisture permeability and a B-1 moisture permeably both of which are not less than 5,000 g/m2ยท24 h and a water pressure resistance of not lower than 5,000 mmH2O.Type: ApplicationFiled: February 22, 2011Publication date: December 20, 2012Applicant: SEIREN CO., LTD.Inventors: Yoshiyuki Yamada, Katsumi Sakamoto, Yoshiharu Kato
-
Publication number: 20120163101Abstract: A memory interface circuit includes a gating circuit that starts detection of a logic level of a data strobe signal in accordance with a data read command. A clamp circuit clamps the data strobe signal to a first logic level after the data read command is issued. A detection circuit detects a logic level of the data strobe signal, which is driven by the memory, in accordance with the data read command.Type: ApplicationFiled: November 18, 2011Publication date: June 28, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Yoshiharu KATO
-
Publication number: 20120132363Abstract: A moisture-permeable waterproof fabric which has a well-balanced combination of moisture permeability and waterproofing properties and has excellent strength, in particular, tensile strength, is provided without increasing environmental burden. A synthetic-polymer solution comprising a synthetic polymer consisting mainly of a polyurethane, fine inorganic particles, and a polar organic solvent is applied to one surface of a fibrous fabric and then brought into contact with a gaseous phase in which waterdrops having an average particle diameter of 1-30 ?m have been evenly dispersed, thereby making the synthetic polymer semisolid. The fabric is then immersed in water to completely solidify the polymer and thereby obtain a moisture-permeable waterproof fabric comprising the fibrous fabric and, united to one surface thereof, a microporous film of a single-layer structure comprising the synthetic polymer consisting mainly of a polyurethane (the number of micropores having a pore diameter of 0.Type: ApplicationFiled: April 28, 2010Publication date: May 31, 2012Applicant: SEIREN CO., LTD.Inventors: Yoshiharu Kato, Katsumi Sakamoto
-
Patent number: 8023353Abstract: The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.Type: GrantFiled: June 18, 2010Date of Patent: September 20, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Masami Nakashima, Yoshiharu Kato, Kazufumi Komura
-
Patent number: 7827468Abstract: A volatile memory has a volatile additional area for storing an error correction code for a nonvolatile memory. Data stored in the nonvolatile memory are transferred to the volatile memory together with the error correction code without making an error correction. Thus, data transfer time from the nonvolatile memory to the volatile memory can be shortened. As a result, it is possible to shorten the time from beginning of the data transfer from the nonvolatile memory to the volatile memory to a point at which data becomes accessible.Type: GrantFiled: October 19, 2006Date of Patent: November 2, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Yoshiharu Kato, Yoshihiro Takemae, Toshio Ogawa, Tetsuhiko Endoh, Yoshinori Okajima
-
Publication number: 20100254208Abstract: The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.Type: ApplicationFiled: June 18, 2010Publication date: October 7, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masami Nakashima, Yoshiharu Kato, Kazufumi Komura
-
Patent number: 7764559Abstract: The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh operation and an external access operation are being executed independently of each other, a refresh address counter outputs a refresh address Add(C) and inputs predetermined high-order bits thereof to a refresh-thinning-out control as a high-order refresh address Add(C) (m), where judgment as to whether the refresh operation is performed, is made. A refresh permission signal RFEN corresponding to the result of judgment is inputted to a word driver to activate and control the word driver. The process of judgment by the refresh-thinning-out control circuit can be embedded in an access time of a row system.Type: GrantFiled: March 8, 2007Date of Patent: July 27, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Masami Nakashima, Yoshiharu Kato, Kazufumi Komura
-
Publication number: 20090261853Abstract: An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC0 and DC1 produce delay data strobe signals IDQS0 and IDQS1 delayed by delay times DT0 and DT1. Outputted as a reverse signal from the inverter INV0, is a reverse data strobe signal RIDQS0 in response to the delay data strobe signal IDQS0, and delayed by an allowable delay time IT. Inputted into the NAND gate ND0, are the reverse data strobe signal RIDQS0 and the delay data strobe signal IDQS1. When, in comparison with the phase of the delay data strobe signal IDQS0, the phase of the delay data strobe signal IDQS1 is delayed by the allowable delay time IT or more, a pulse signal PL0 is not outputted from the NAND gate ND0.Type: ApplicationFiled: June 26, 2009Publication date: October 22, 2009Applicant: FUJITSU LIMITEDInventor: Yoshiharu KATO
-
Patent number: 7579875Abstract: This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal attains an inactive state. The interface circuit has a comparing portion for comparing the potential of the DQS with a threshold potential VREFH which is a potential that is different from the intermediate potential VM.Type: GrantFiled: October 4, 2006Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics Ltd.Inventor: Yoshiharu Kato
-
Patent number: 7562335Abstract: An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC0 and DC1 produce delay data strobe signals IDQS0 and IDQS1 delayed by delay times DT0 and DT1. Outputted as a reverse signal from the inverter INV0, is a reverse data strobe signal RIDQS0 in response to the delay data strobe signal IDQS0, and delayed by an allowable delay time IT. Inputted into the NAND gate ND0, are the reverse data strobe signal RIDQS0 and the delay data strobe signal IDQS1. When, in comparison with the phase of the delay data strobe signal IDQS0, the phase of the delay data strobe signal IDQS1 is delayed by the allowable delay time IT or more, a pulse signal PL0 is not outputted from the NAND gate ND0.Type: GrantFiled: October 19, 2006Date of Patent: July 14, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Yoshiharu Kato
-
Patent number: 7551612Abstract: A switch station including an ATM switch; a memory storing control data for operations of the switch station; an intra-station device, accommodating a subscriber line, performing communication operation on subscriber ATM cell; a control processor generating control information in link access protocol (LAP) format; and an interface unit converting LAP control information into ATM cell to the intra-station device through the ATM switch, wherein the control information is communicated according to LAP, the intra-station device receives the control information and transmits a direct memory access request to obtain control data stored in the memory, the interface unit obtains and converts the data format of the control data into ATM cell to transmit to the intra-station device through the switch, and the intra-station device performs the communication operation on the subscriber ATM cell based on the control data received through the switch.Type: GrantFiled: March 26, 1999Date of Patent: June 23, 2009Assignee: Fujitsu LimitedInventors: Yasusi Kobayashi, Yoshihiro Watanabe, Hiroshi Nishida, Masami Murayama, Naoyuki Izawa, Yasuhiro Aso, Yoshihiro Uchida, Hiromi Yamanaka, Jin Abe, Yoshihisa Tsuruta, Yoshiharu Kato, Satoshi Kakuma, Shiro Uriu, Noriko Samejima, Eiji Ishioka, Shigeru Sekine, Yoshiyuki Karakawa, Atsushi Kagawa, Mikio Nakayama, Miyuki Kawataka, Satoshi Esaka, Nobuyuki Tsutsui, Fumio Hirase, Atsuko Suzuki, Shouji Kohira, Kenichi Okabe, Takashi Hatano, Yasuhiro Nishikawa, Jun Itoh, Shinichi Araya
-
Patent number: 7495990Abstract: It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k?1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.Type: GrantFiled: June 4, 2007Date of Patent: February 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kazufumi Komura, Yoshiharu Kato, Satoru Kawamoto