Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.

Abstract: A technique for evaluating a semiconductor chip is provided. The semiconductor chip is mounted on a mount substrate, the semiconductor chip laminating on one surface of a silicone substrate, at least any of a metal wiring film 101 serving as a resistance temperature detector made up of multiple regions and a metal wiring film 102 serving as a heater made up of one or more regions, and an electrode 103 for connecting the metal wiring film 101 and the metal wiring film 102 with the mount substrate. Then, the metal wiring film 101 is electrically connected with an ammeter and a voltmeter, and the metal wiring film 102 is electrically connected with a power source, thereby providing an evaluation system which is capable of evaluating temperature measurement, heating, and temperature profile in each of the regions on the semiconductor chip.

Abstract: This invention provides: an exposure apparatus and exposure method based on a maskless exposure technique which uses a two-dimensional optical modulator, in which maskless exposure technique, the exposure apparatus and exposure method employ a first irradiation source optics for drawing a pattern based on exposure pattern data, and a second irradiation source optics for irradiating an energy ray onto a desired area of space on a region inclusive of a region in which the pattern has been drawn; and a method of manufacturing a wiring Substrate (Board); thus, highly accurate pattern forming based on the exposure pattern data is achieved at high throughput and at low costs.

Abstract: The mask-less exposure apparatus includes: a stage which moves with the substrate having a photosensitive resin layer with sensitivity to ultraviolet radiation formed thereon; a first light source for emitting light containing a wavelength component in the wavelength range of 300 to 410 nm; a first light irradiation optical system for modulating a radiant flux emitted from the first light source based on data of a desired exposure pattern to image a pattern on the photosensitive resin layer; a second light source for emitting light containing a wavelength component in the wavelength range of 450 to 2500 nm; and a second light irradiation optical system for guiding a radiant flux emitted from the second light source to a second light irradiation area that is set so as to include at least a first light irradiation area.

Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.

Abstract: A disk device has a small size, a small thickness, a high efficiency, a small degree of vibration and a small level of noise. In one embodiment, the disk device comprises a disk for storing information and a disk drive for driving the disk. The disk drive includes a rotor portion mounting an annular permanent magnet on the outer peripheral portion thereof, and a stator portion disposed on the outer side in the radial direction of the annular permanent magnet. The stator portion is constituted by a wiring board provided with a stator core formed by laminating magnetic metal plates in a radial manner and a coil that is so formed as to surround the stator core while electrically connecting wiring layers and through hole portions. The coil is so formed that among the envelopes connecting the outermost peripheral surfaces of the coil in the radial direction, the neighboring envelops and intersect at an inner position in the radial direction.

Abstract: The present invention provides a pattern formation method comprising a step of forming on a substrate a film of a first photosensitive material having low sensitivity to a light beam with a main wavelength at h-line emitted from a mask-less drawing exposure apparatus but having high sensitivity to an energy light beam containing ultraviolet light; a step of forming on the first photosensitive material a film of a second photosensitive material having higher sensitivity to a light beam with the main wavelength at h-line; a step of drawing a second pattern on the second photosensitive material with the mask-less direct drawing exposure apparatus; a step of developing the second photosensitive material; and a step of exposing to a light beam the second photosensitive material with the second pattern formed thereon and the first photosensitive material in batch to form a target first pattern on the first photosensitive material.

Abstract: The present invention sufficiently secures conductor component content ratio in wiring formed on a multilayer circuit board and increases reliability by fabricating the multilayer circuit board by steps of drawing wiring precursor patterns containing a paste of compound for forming wiring conductor containing (a) superfine metal particles (metal nanoparticles) whose average particle size is 1-10 nm; (b) an organic coating compound coated on the surface of the superfine metal particle in the film thickness of 1-10 nm; (c) a latent reactive organic compound reacting with the organic coating compound in the range of 100-250° C., (d) metal particles whose average particle size is 0.5-10 ?m, and (e) dispersion medium that stably disperses components (a) through (d) on a substrate by screen printing, sintering by heating the patterns to 100-250° C., and electrochemically treating the patterns to allow the conductor to deposit in a desired cross-sectional area in the inside.

Abstract: The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

Abstract: The present invention sufficiently secures conductor component content ratio in wiring formed on a multilayer circuit board and increases reliability by fabricating the multilayer circuit board by steps of drawing wiring precursor patterns containing a paste of compound for forming wiring conductor containing (a) superfine metal particles (metal nanoparticles) whose average particle size is 1-10 nm; (b) an organic coating compound coated on the surface of the superfine metal particle in the film thickness of 1-10 nm; (c) a latent reactive organic compound reacting with the organic coating compound in the range of 100-250° C., (d) metal particles whose average particle size is 0.5-10 ?m, and (e) dispersion medium that stably disperses components (a) through (d) on a substrate by screen printing, sintering by heating the patterns to 100-250° C., and electrochemically treating the patterns to allow the conductor to deposit in a desired cross-sectional area in the inside.

Abstract: This invention provides: an exposure apparatus and exposure method based on a maskless exposure technique which uses a two-dimensional optical modulator, in which maskless exposure technique, the exposure apparatus and exposure method employ a first irradiation source optics for drawing a pattern based on exposure pattern data, and a second irradiation source optics for irradiating an energy ray onto a desired area of space on a region inclusive of a region in which the pattern has been drawn; and a method of manufacturing a wiring Substrate (Board); thus, highly accurate pattern forming based on the exposure pattern data is achieved at high throughput and at low costs.

Abstract: A disk device has a small size, a small thickness, a high efficiency, a small degree of vibration and a small level of noise. In one embodiment, the disk device comprises a disk for storing information and a disk drive for driving the disk. The disk drive includes a rotor portion mounting an annular permanent magnet on the outer peripheral portion thereof, and a stator portion disposed on the outer side in the radial direction of the annular permanent magnet. The stator portion is constituted by a wiring board provided with a stator core formed by laminating magnetic metal plates in a radial manner and a coil that is so formed as to surround the stator core while electrically connecting wiring layers and through hole portions. The coil is so formed that among the envelopes connecting the outermost peripheral surfaces of the coil in the radial direction, the neighboring envelops and intersect at an inner position in the radial direction.

Abstract: The mask-less exposure apparatus includes: a stage which moves with the substrate having a photosensitive resin layer with sensitivity to ultraviolet radiation formed thereon; a first light source for emitting light containing a wavelength component in the wavelength range of 300 to 410 nm; a first light irradiation optical system for modulating a radiant flux emitted from the first light source based on data of a desired exposure pattern to image a pattern on the photosensitive resin layer; a second light source for emitting light containing a wavelength component in the wavelength range of 450 to 2500 nm; and a second light irradiation optical system for guiding a radiant flux emitted from the second light source to a second light irradiation area that is set so as to include at least a first light irradiation area.

Abstract: A semiconductor device which includes a semiconductor chip, an insulating film formed on the semiconductor chip, a plurality of projected stress relaxation materials formed on the insulating film, projected electrodes covering at least tops of the stress relaxation materials, and wiring lines for electrically connecting the projected electrodes and element electrodes of the semiconductor chip.

Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide ?-ray shielding of the semiconductor device.

Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: A semiconductor module, comprising a wiring substrate on which wiring is formed, a semiconductor device electrically connected to the wiring formed on the wiring substrate, and an external connection terminal arranged on the semiconductor device mounted side of the wiring substrate so as to be a connected portion between the wiring and the outside electrically connected thereto, wherein there is formed an insulating resin layer thicker than the semiconductor device between the wiring substrate and the external connection terminal.

Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.