Abstract: The present invention sufficiently secures conductor component content ratio in wiring formed on a multilayer circuit board and increases reliability by fabricating the multilayer circuit board by steps of drawing wiring precursor patterns containing a paste of compound for forming wiring conductor containing (a) superfine metal particles (metal nanoparticles) whose average particle size is 1-10 nm; (b) an organic coating compound coated on the surface of the superfine metal particle in the film thickness of 1-10 nm; (c) a latent reactive organic compound reacting with the organic coating compound in the range of 100-250° C., (d) metal particles whose average particle size is 0.5-10 ?m, and (e) dispersion medium that stably disperses components (a) through (d) on a substrate by screen printing, sintering by heating the patterns to 100-250° C., and electrochemically treating the patterns to allow the conductor to deposit in a desired cross-sectional area in the inside.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A semiconductor device having a semiconductor element is obtained by cutting a semiconductor wafer, having an electrode pad formed on one side thereof, along a scribe line. The semiconductor device has a semiconductor element protective layer on the semiconductor element so as to form an opening above the pad, a stress cushioning layer on the layer so as to form an opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and a conductor protective layer on the layer. The layer, the layer, and the conductor protective layer form respective end faces on the end surface of the semiconductor element inside the scribe line and expose a surface of the semiconductor element from the end face of the end surface to a point inside of the scribe line, thereby to expose the scribe line.

Abstract: A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.

Abstract: The fabricating method of a circuit board by the present invention draws a desired pattern of an etching resist endurable to form a fine wiring on the circuit board by a paste sintered on a substrate by performing the steps in order of (a) fabricating the paste (etching resist precursor compound) comprising a superfine metal particle having an average particle size of 1 to 10 nm coated by an organic coating compound having a film thickness of 1 to 10 nm, a latent curing organic compound reacting to the superfine metal particle in the range of 100 to 250° C., and a dispersion medium capable of stably dispersing these components, (b) transferring this paste on a substrate by either of a relief printing, an intaglio printing, an offset printing, or a screen printing, and (c) sintering the paste by heating this substrate to 100 to 250° C.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A semiconductor apparatus comprising a semiconductor device, an electrically insulating layer formed on the semiconductor device, and an external connection terminal formed on the electrically insulating layer and electrically connected to an electrode of the semiconductor device, wherein a power/ground line and a signal line in a region of from an edge of the electrically insulating layer to a uniform-thickness flat portion of the electrically insulating layer are different in kind of wiring pattern from each other.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

Abstract: The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring comprising a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide &agr;-ray shielding of the semiconductor device.

Abstract: A multi-chip module has semiconductor devices and a wiring substrate for mounting the semiconductor devices, in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.

Abstract: In the re-wiring formation process of a WLCSP, at least some of the re-wiring lines 3 that connect the bonding pads 1 and bump pads 2 of the semiconductor chips are formed using a photolithographic process that does not use a photomask. In this re-wiring formation process, standard portions are formed by development following photomask exposure, and portions that are to be designed corresponding to customer specifications are subjected to additional development following additional maskless exposure in the final stage.

Abstract: A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Abstract: A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device.

Abstract: There are provided a high density and low manufacturing cost wiring board with high reliability in connection, a semiconductor device and a producing method therefor. The invention relates to a wiring board comprising a board having an electrode and being coated with an insulation layer with a hole for exposing the electrode; a wiring consisting of a Cr or Ti layer, which is connected to the electrode and closely contacts with the insulation layer, and of a Cu layer which is closely contacts with the Cr or Ti layer; a protective film which covers the wiring and is provided with another hole for soldering; and a solder for the outer connection which is mounted in the both holes and brought to diffuse into the Cu layer to produce an alloy, and brought to reach the Cr or Ti layer thereby connecting the solder to the Cr or Ti layer.

Abstract: Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260° C. in order to prevent the variance of the refresh times of memory cells.

Abstract: Forming solder bumps each having a constant height by surely supplying onto each of electrode pads a solder ball corresponding to a predetermined volume while omitting Au plating performed on the electrode pads onto which the solder bumps are to be formed. For achieving the forming of the solder bumps, the adhesive film is formed instead of the Au plating, the adhesive film being used as an oxidation-preventing film and as film for temporarily fixing each of the solder balls, the solder balls being supplied by stencil mask or the vacuum adsorbing mask.

Abstract: A semiconductor apparatus includes a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus. A first electrically insulating layer is formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer. A second electrically insulating layer is formed on said first insulating layer, and external connection terminals are formed on said second insulating layer. A wiring is formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer is formed on said second insulating layer and on said wiring. Particles are provided in the second insulating layer to control a shape of said second insulating layer.

Abstract: A multi-chip module including semiconductor devices and a wiring substrate for mounting the semiconductor devices in which the wiring substrate comprises a glass substrate having holes formed by sand blasting and a wiring layer formed on the surface of the glass substrate and having wiring and an insulation layer.

Abstract: Forming solder bumps each having a constant height by surely supplying onto each of electrode pads a solder ball corresponding to a predetermined volume while omitting Au plating performed on the electrode pads onto which the solder bumps are to be formed. For achieving the forming of the solder bumps, the adhesive film is formed instead of the Au plating, the adhesive film being used as an oxidation-preventing film and as film for temporarily fixing each of the solder balls, the solder balls being supplied by stencil mask or the vacuum adsorbing mask.