Patents by Inventor Yoshihiro Nakata

Yoshihiro Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10483195
    Abstract: A resin board includes: a resin layer and a through electrode buried in the resin layer, wherein the through electrode has an electrode surface exposed from a front surface or a back surface of the resin layer and a lateral surface, and the electrode surface and the lateral surface form an obtuse angle.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: November 19, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yasushi Kobayashi, Yoshihiro Nakata, Yoshikatsu Ishizuki, Daijiro Ishibashi, Shinya Sasaki
  • Patent number: 10477043
    Abstract: A document processing apparatus includes an image processing unit, a target determination unit, a text reading unit, and a keyword extraction unit. The image processing unit processes an image. The target determination unit determines whether an image that is a target of a process executed by the image processing unit is to be used as a keyword extraction target. The text reading unit reads a text from the image processed by the image processing unit. The keyword extraction unit extracts a keyword from the text read by the text reading unit from an image determined to be a keyword extraction target by the target determination unit.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: November 12, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Kenji Kuroishi, Chigusa Nakata, Hiroshi Honda, Eiji Nishi, Yoshihiro Sekine, Hiroshi Mikuriya, Takeshi Furuya, Ryuichi Ishizuka
  • Publication number: 20190312122
    Abstract: An electronic component includes: a conductor portion containing a first element; a compound layer disposed around the conductor portion and containing a second element and a third element which are different from the first element; and an isolation layer, disposed between the conductor portion and the compound layer and containing a fourth element which is different from the first element, the second element, and the third element, to isolate the first element in the conductor portion from the second element and the third element outside the conductor portion.
    Type: Application
    Filed: June 25, 2019
    Publication date: October 10, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masaru Morita, Yoshihiro Nakata
  • Publication number: 20190247978
    Abstract: A manufacturing method for a high pressure tank includes preparing a liner including a cylindrical body portion and a pair of side end portions, forming a reinforcing layer by winding fiber-reinforced resin around an outer peripheral surface of the liner, carrying out shot peening by shooting a shot material towards an inner periphery region of a boundary between the body portion and each of the side end portions, and carrying out autofrettage after the reinforcing layer is formed and the shot peening is carried out. The autofrettage is carried out by applying internal pressure to the liner such that the liner is plastically deformed and then eliminating the internal pressure such that compression stress is applied to the liner.
    Type: Application
    Filed: February 7, 2019
    Publication date: August 15, 2019
    Inventor: Yoshihiro NAKATA
  • Patent number: 10303138
    Abstract: An equipment control system includes an equipment control device that controls equipment provided in an office room, and an external control device that is provided outside the office room and controls the equipment provided in the office room via the equipment control device, wherein when a predetermined condition is satisfied, a control device that controls the equipment is switched from one of the equipment control device and the external control device to the other.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 28, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Yoshihiro Sekine, Chigusa Nakata, Hiroshi Honda, Eiji Nishi, Kenji Kuroishi, Hiroshi Mikuriya, Takeshi Furuya, Ryuichi Ishizuka, Keita Sakakura
  • Publication number: 20190047142
    Abstract: A modularized externally-driven joint structure can be used for general purposes. An externally-driven joint structure: includes a shaft member that extends in an axial direction; and a number of rotatable members that are arranged along the axial direction, and are coupled with each other by the shaft member in an axially rotatable manner. Each of the rotatable members includes a pair of face portions that face each other in the axial direction, a side wall portion that is arranged along the outer circumferential edges of the pair of face portions, and at least one coupling portion that is arranged at the face portions or the side wall portion, and is coupled with a link member constituting a link of a robot.
    Type: Application
    Filed: February 10, 2017
    Publication date: February 14, 2019
    Inventors: Tomoyuki Noda, Yoshihiro Nakata, Hiroshi Ishiguro, Jun Morimoto
  • Patent number: 10128731
    Abstract: A linear vernier motor includes a stator and a mover. The stator extends in a first direction. The mover extends in the first direction and a pole interval is different from that of the stator. At least one of the stator and the mover includes: a plurality of permanent magnets arranged in the first direction and a plurality of yokes arranged in the first direction. Each of the plurality of yokes is arranged between adjacent permanent magnets. The plurality of permanent magnets is magnetized to the first direction and magnetization orientations of adjacent permanent magnets are opposite to each other.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: November 13, 2018
    Assignees: MITSUBISHI HEAVY INDUSTRIES, LTD., OSAKA UNIVERSITY
    Inventors: Ryota Hiura, Katsuhiro Hirata, Hiroshi Ishiguro, Yoshihiro Nakata
  • Publication number: 20170365545
    Abstract: A resin board includes: a resin layer and a through electrode buried in the resin layer, wherein the through electrode has an electrode surface exposed from a front surface or a back surface of the resin layer and a lateral surface, and the electrode surface and the lateral surface form an obtuse angle.
    Type: Application
    Filed: June 12, 2017
    Publication date: December 21, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Yasushi Kobayashi, Yoshihiro NAKATA, Yoshikatsu Ishizuki, Daijiro Ishibashi, Shinya Sasaki
  • Publication number: 20170198728
    Abstract: [Object] To provide a compact, high-output actuator device allowing force control. [Solution] An actuator device 1000 includes an electromagnetic coil member 110 provided over a prescribed width on an outer circumference of a cylinder 100, and a movable element 200 slidable as a piston in the cylinder 100. The movable element 200 has a magnetic member 202, and is moved relatively by excitation of the electromagnetic coil member 110. Fluid is supplied to first and second chambers 106a and 106b such that when the movable element 200 is to be moved relatively, the movable element 200 is driven in the same direction.
    Type: Application
    Filed: May 27, 2015
    Publication date: July 13, 2017
    Applicants: ADVANCED TELECOMMUNICATIONS RESEARCH INSTITUTE INTERNATIONAL, OSAKA UNIVERSITY
    Inventors: Tomoyuki NODA, Yoshihiro NAKATA, Hiroshi ISHIGURO, Jun MORIMOTO
  • Publication number: 20160381795
    Abstract: An electronic device includes: a substrate; a Cu-containing wiring layer formed over the substrate; a barrier metal layer that covers a surface of the Cu-containing wiring layer and suppresses diffusion of Cu; and a coating insulating layer that covers the barrier metal layer, wherein the barrier metal layer has a void that does not reach the Cu-containing wiring layer, and the void is filled with the coating insulating layer.
    Type: Application
    Filed: May 23, 2016
    Publication date: December 29, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Junya Ikeda, Miwa Kozawa, Tsuyoshi Kanki, Yoshihiro Nakata
  • Patent number: 9496222
    Abstract: A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive portion formed over a surface of the first insulating film, and a second insulating film which covers the principal plane of the substrate, the first insulating film, and the conductive portion and whose moisture resistance is higher than moisture resistance of the first insulating film. The first insulating film is placed between the substrate and the conductive portion to prevent the generation of parasitic capacitance. The first insulating film is covered with the second insulating film whose moisture resistance is higher than the moisture resistance of the first insulating film. The second insulating film prevents the first insulating film from absorbing moisture.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: November 15, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Junichi Kon, Yoshihiro Nakata, Kozo Makiyama
  • Patent number: 9354517
    Abstract: A resist composition includes: a solvent; and a resin in the solvent, the resin being prepared by the hydrolysis and condensation of an alkoxy group-containing compound that contains an alkoxy group bound to a silicon atom or a germanium atom in the presence of an acid or an alkali, wherein a portion of the resist composition irradiated with an energy radiation is insoluble in a developing solution.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: May 31, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Junichi Kon, Yoshihiro Nakata
  • Patent number: 9263326
    Abstract: After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: February 16, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi
  • Publication number: 20150243555
    Abstract: After a copper interconnection is formed above a substrate, a surface of the copper interconnection is activated by performing acid cleaning. Thereafter, the substrate is immersed in a BTA (Benzo triazole) aqueous solution to form a protection film covering the surface of the copper interconnection. At this time, Cu—N—R bonds (R is an organic group) are formed in grain boundary portions in the surface of the copper interconnection. Thereafter, the protection film is removed by performing alkaline cleaning. The Cu—N—R bonds remain in the grain boundary portions in the surface of the copper interconnection even after the protection film is removed. Subsequently, the surface of the copper interconnection is subjected to an activation process, and a barrier layer is formed thereafter by electroless-plating the surface of the copper interconnection with NiP or CoWP.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 27, 2015
    Inventors: Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi
  • Publication number: 20150135472
    Abstract: A substrate processing apparatus comprising a processing vessel evacuated by an evacuation system and accommodating therein a stage configured to hold a substrate; a superheated steam generator configured to supply a superheated steam to said processing vessel; a gas supplying apparatus supplying an inert gas or a reducing gas to said processing vessel; an oxygen concentration level measuring device configured to measure an oxygen concentration level in said processing vessel; and a heating mechanism provided in said stage and configured to heat said substrate on said stage to a temperature of said superheated steam to which said substrate is exposed, wherein said superheated steam generator supplies said superheated steam to said processing vessel with a temperature higher than a temperature of said substrate on the stage.
    Type: Application
    Filed: December 22, 2014
    Publication date: May 21, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Yoshihiro Nakata
  • Patent number: 8956967
    Abstract: A method of forming an interconnection structure includes forming an opening in an insulation film by a dry etching process that uses an etching gas containing fluorine; cleaning a bottom surface and a sidewall surface of the opening by exposing to a superheated steam; covering the bottom surface and the sidewall surface of the opening with a barrier metal film; depositing a conductor film on the insulation film via the barrier metal film to fill the opening with the conductor film; forming an interconnection pattern by the conductor film in the opening by polishing the conductor film and the barrier metal film underneath the conductor film by a chemical mechanical polishing process until a surface of the insulation film is exposed.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata
  • Patent number: 8872040
    Abstract: A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Kanki, Shoichi Suda, Yoshihiro Nakata
  • Publication number: 20140264826
    Abstract: A semiconductor device has a structure including a substrate, a first insulating film formed over a part of a principal plane of the substrate, a conductive portion formed over a surface of the first insulating film, and a second insulating film which covers the principal plane of the substrate, the first insulating film, and the conductive portion and whose moisture resistance is higher than moisture resistance of the first insulating film. The first insulating film is placed between the substrate and the conductive portion to prevent the generation of parasitic capacitance. The first insulating film is covered with the second insulating film whose moisture resistance is higher than the moisture resistance of the first insulating film. The second insulating film prevents the first insulating film from absorbing moisture.
    Type: Application
    Filed: February 6, 2014
    Publication date: September 18, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Junichi Kon, Yoshihiro NAKATA, Kozo Makiyama
  • Publication number: 20140272706
    Abstract: A resist composition includes: a solvent; and a resin in the solvent, the resin being prepared by the hydrolysis and condensation of an alkoxy group-containing compound that contains an alkoxy group bound to a silicon atom or a germanium atom in the presence of an acid or an alkali, wherein a portion of the resist composition irradiated with an energy radiation is insoluble in a developing solution.
    Type: Application
    Filed: November 13, 2013
    Publication date: September 18, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Junichi Kon, Yoshihiro NAKATA
  • Patent number: 8791561
    Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: July 29, 2014
    Assignees: Fujitsu Limited, Shinko Electric Industries Co., Ltd.
    Inventors: Sadahiro Kishii, Tsuyoshi Kanki, Yoshihiro Nakata, Yasushi Kobayashi, Masato Tanaka, Akio Rokugawa